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11.发明授权Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method 失效使用分层分层设计流程设计集成电路的方法和采用该方法的装置公开(公告)号：US08539419B2
公开(公告)日：2013-09-17
申请号：US13421710
申请日：2012-03-15
申请人： Vishwas M. Rao , James C. Parker
发明人： Vishwas M. Rao , James C. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5045 , G06F2217/84
摘要： Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.
摘要翻译： 公开了设计IC和分层设计流发生器的方法。 在一个实施例中，该方法包括：（1）在设备处接收用于IC设计的定时和物理约束，（2）建立分层设计流程，以提供采用该设备的IC设计的实现，以及（3） 设计流入后期设计流程部分和采用该装置的早期设计流程部分，其中后期设计流程部分对于不同的设计流程方法基本相同。
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12.发明授权Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method 失效使用分层分层设计流程设计集成电路的方法和采用该方法的装置公开(公告)号：US08239805B2
公开(公告)日：2012-08-07
申请号：US12510104
申请日：2009-07-27
申请人： Vishwas M. Rao , James C. Parker
发明人： Vishwas M. Rao , James C. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5045 , G06F2217/84
摘要： Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor.
摘要翻译： 公开了设计IC和分层设计流发生器的方法。 在一个实施例中，一种方法包括：（1）将IC的设计实现流程划分为后期设计流程部分和采用处理器的早期设计流程部分，（2）将后期设计流程部分的组件和早期设计 流动部分进入功能块实现部分和采用该处理器的顶层实现部分，（3）在早期设计流程部分和后期设计流程部分中使用功能块实现部分和顶层实现部分之间的依赖关系进行对准 处理器和（4）基于采用处理器的早期和晚期设计流程部分实现IC的布局。
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13.发明申请NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW 失效用于分层设计中的时序关闭的新建模方法利用设计流程的水平和垂直方面的分离公开(公告)号：US20120095746A1
公开(公告)日：2012-04-19
申请号：US12905301
申请日：2010-10-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.
摘要翻译： 本文公开了设计集成电路和集成电路块的模型的方法，电子设计自动化工具，装置和计算机可读介质。 在一个实施例中，设计集成电路的方法包括：（1）利用集成电路的设计者输入产生集成电路的定时预算，（2）使用定时预算为集成电路的块建立设计约束， （3）使用设计约束创建用于块的输入和输出定时预算，（4）将基于设计者知识的集成电路的实现信息与输入和输出定时预算组合以产生更新的输入和输出定时预算; 5）基于更新的输入和输出定时预算生成块的模型。
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14.发明授权Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods 有权使用上下文相关和渐进式规则设计集成电路的方法和采用其中一种方法的装置公开(公告)号：US08127264B2
公开(公告)日：2012-02-28
申请号：US12510122
申请日：2009-07-27
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.
摘要翻译： 公开了设计IC和装置的方法。 在一个实施例中，一种方法包括：（1）创建用于IC设计的功能块的功能电路，（2）验证所述功能电路满足所述IC设计的规则集，其中所述规则集是基于上下文的 相对于所述设计流程，（3）基于功能电路合成逻辑电路; （4）验证逻辑电路满足规则集; （5）实现逻辑电路的物理布局; 和（6）验证物理布局满足规则集，其中该方法的每个步骤由至少一个EDA工具执行。
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15.发明申请SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS 失效用于标准化数据创建，分析和比较半导体技术节点特性的系统基准系统和方法公开(公告)号：US20110307852A1
公开(公告)日：2011-12-15
申请号：US13212427
申请日：2011-08-18
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.
摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计用于时钟路径，数据路径和触发器路径的代表性基准电路，（2）建立用于代表性基准的延迟和功率的至少一个标准敏感度和测量规则 电路和技术节点的角落，（3）通过遍历角度范围进行扫描并以预定间隔跨越角落，（4）从模拟中提取数据，（5）将数据写入数据库和（ 6）解析和解释数据以产生至少一个报告。
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16.发明申请METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD 失效设计采用分层分层设计流程的集成电路的方法和采用该方法的设备公开(公告)号：US20110022998A1
公开(公告)日：2011-01-27
申请号：US12510104
申请日：2009-07-27
申请人： Vishwas M. Rao , James C. Parker
发明人： Vishwas M. Rao , James C. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5045 , G06F2217/84
摘要： Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor.
摘要翻译： 公开了设计IC和分层设计流发生器的方法。 在一个实施例中，一种方法包括：（1）将IC的设计实现流程划分为后期设计流程部分和采用处理器的早期设计流程部分，（2）将后期设计流程部分的组件和早期设计 流动部分进入功能块实现部分和采用该处理器的顶层实现部分，（3）在早期设计流程部分和后期设计流程部分中使用功能块实现部分和顶层实现部分之间的依赖关系进行对准 处理器和（4）基于采用处理器的早期和晚期设计流程部分实现IC的布局。
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17.发明授权Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow 失效分层设计中的时序收敛的建模方法利用设计流程的水平和垂直方面的分离公开(公告)号：US08341573B2
公开(公告)日：2012-12-25
申请号：US12905301
申请日：2010-10-15
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.
摘要翻译： 本文公开了设计集成电路和集成电路块的模型的方法，电子设计自动化工具，装置和计算机可读介质。 在一个实施例中，设计集成电路的方法包括：（1）利用集成电路的设计者输入产生集成电路的定时预算，（2）使用定时预算为集成电路的块建立设计约束， （3）使用设计约束创建用于块的输入和输出定时预算，（4）将基于设计者知识的集成电路的实现信息与输入和输出定时预算组合以产生更新的输入和输出定时预算; 5）基于更新的输入和输出定时预算生成块的模型。
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18.发明授权Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics 失效系统基准系统和方法，用于标准化数据创建，分析和比较半导体技术节点特性公开(公告)号：US08307324B2
公开(公告)日：2012-11-06
申请号：US13212427
申请日：2011-08-18
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.
摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计用于时钟路径，数据路径和触发器路径的代表性基准电路，（2）建立用于代表性基准的延迟和功率的至少一个标准敏感度和测量规则 电路和技术节点的角落，（3）通过遍历角度范围进行扫描并以预定间隔跨越角落，（4）从模拟中提取数据，（5）将数据写入数据库和（ 6）解析和解释数据以产生至少一个报告。
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19.发明申请METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD 失效设计采用分层分层设计流程的集成电路的方法和采用该方法的设备公开(公告)号：US20120174048A1
公开(公告)日：2012-07-05
申请号：US13421710
申请日：2012-03-15
申请人： Vishwas M. Rao , James C. Parker
发明人： Vishwas M. Rao , James C. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5045 , G06F2217/84
摘要： Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.
摘要翻译： 公开了设计IC和分层设计流发生器的方法。 在一个实施例中，该方法包括：（1）在设备处接收用于IC设计的定时和物理约束，（2）建立分层设计流程，以提供采用该设备的IC设计的实现，以及（3） 设计流入后期设计流程部分和采用该装置的早期设计流程部分，其中后期设计流程部分对于不同的设计流程方法基本相同。
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20.发明申请METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS 有权设计采用预先确定的时序实时时钟延迟和集成电路设计工具的集成电路的方法公开(公告)号：US20120011484A1
公开(公告)日：2012-01-12
申请号：US12831038
申请日：2010-07-06
申请人： Vishwas M. Rao , James C. Parker
发明人： Vishwas M. Rao , James C. Parker
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/62
摘要： A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.
摘要翻译： 本文公开了一种设计集成电路，EDA工具，装置和计算机可读介质的方法。 在一个实施例中，该方法包括：（1）生成表示集成电路的时钟插入延迟值的一组约束方程作为变量，（2）基于约束方程确定每个时钟插入延迟值的边界;以及 （3）基于用于驱动所述集成电路的设计以关闭的边界产生一组关闭命令，其中所述方法的每个步骤由至少一个EDA工具执行。
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