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1.发明申请SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 审中-公开用于分析和比较采用电压调节的集成电路和集成电路的优化方法的系统，正则化公制公开(公告)号：US20130055175A1
公开(公告)日：2013-02-28
申请号：US13599549
申请日：2012-08-30
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist.
摘要翻译： 本文提供了设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生功能IC设计，（2）确定功能IC设计的目标时钟速率，（3）从满足目标时钟速率的功能IC设计生成网表（ 4）从网表确定无单位性能/功率量化器，（5）尝试通过改变网表中的至少一些非关键路径中的速度，面积和功率消耗中的至少一个来增加无单位性能/功率量化器， 其中所述尝试由处理器执行，并且（6）从所述网表生成所述IC的布局。
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2.发明授权Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby 失效用于分析和比较采用电压缩放的集成电路和由此设计的集成电路的优化技术的系统的归一化度量公开(公告)号：US08281266B2
公开(公告)日：2012-10-02
申请号：US12365010
申请日：2009-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译： 设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压 缩放以实现优化目标电压下的性能目标，如果是，则采用静态电压缩放或自适应电压缩放，（5）使用优化目标电压从功能IC设计中合成布局，满足 通过采用无单位性能/功率量化器作为衡量其优化程度的度量的性能目标，以及（6）在优化目标电压下执行布局的定时签出。
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3.发明申请公开(公告)号：US20100037188A1
公开(公告)日：2010-02-11
申请号：US12365010
申请日：2009-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional design for the IC, (2) determining performance objectives for the IC, (3) determining an optimization target voltage for the IC, (4) determining whether the IC needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the IC is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional IC design that meets the performance objectives by employing a unitless performance/power quantifier as a metric to gauge a degree of optimization thereof and (6) performing a timing signoff of the layout at the optimization target voltage.
摘要翻译： 设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生IC的功能设计，（2）确定IC的性能目标，（3）确定IC的优化目标电压，（4）确定IC是否需要电压 缩放以实现优化目标电压下的性能目标，如果是，则采用静态电压缩放或自适应电压缩放，（5）使用优化目标电压从功能IC设计中合成布局，满足 通过采用无单位性能/功率量化器作为衡量其优化程度的度量的性能目标，以及（6）在优化目标电压下执行布局的定时签出。
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4.发明申请SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS 有权用于标准化数据创建，分析和比较半导体技术节点特性的系统基准系统和方法公开(公告)号：US20090281772A1
公开(公告)日：2009-11-12
申请号：US12365084
申请日：2009-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.
摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计至少一个代表性基准电路，（2）建立用于至少一个代表基准电路的延迟和功率的标准敏感度和测量规则，以及技术节点中的角部（3 ）通过遍历角度范围进行扫描并以预定间隔横跨角落执行模拟，（4）从模拟中提取数据，（5）解析和解释数据以产生至少一个报告。
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5.发明申请NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW 失效用于分层设计中的时序关闭的新建模方法利用设计流程的水平和垂直方面的分离公开(公告)号：US20120095746A1
公开(公告)日：2012-04-19
申请号：US12905301
申请日：2010-10-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.
摘要翻译： 本文公开了设计集成电路和集成电路块的模型的方法，电子设计自动化工具，装置和计算机可读介质。 在一个实施例中，设计集成电路的方法包括：（1）利用集成电路的设计者输入产生集成电路的定时预算，（2）使用定时预算为集成电路的块建立设计约束， （3）使用设计约束创建用于块的输入和输出定时预算，（4）将基于设计者知识的集成电路的实现信息与输入和输出定时预算组合以产生更新的输入和输出定时预算; 5）基于更新的输入和输出定时预算生成块的模型。
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6.发明申请SYSTEMATIC BENCHMARKING SYSTEM AND METHOD FOR STANDARDIZED DATA CREATION, ANALYSIS AND COMPARISON OF SEMICONDUCTOR TECHNOLOGY NODE CHARACTERISTICS 失效用于标准化数据创建，分析和比较半导体技术节点特性的系统基准系统和方法公开(公告)号：US20110307852A1
公开(公告)日：2011-12-15
申请号：US13212427
申请日：2011-08-18
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.
摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计用于时钟路径，数据路径和触发器路径的代表性基准电路，（2）建立用于代表性基准的延迟和功率的至少一个标准敏感度和测量规则 电路和技术节点的角落，（3）通过遍历角度范围进行扫描并以预定间隔跨越角落，（4）从模拟中提取数据，（5）将数据写入数据库和（ 6）解析和解释数据以产生至少一个报告。
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7.发明授权Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow 失效分层设计中的时序收敛的建模方法利用设计流程的水平和垂直方面的分离公开(公告)号：US08341573B2
公开(公告)日：2012-12-25
申请号：US12905301
申请日：2010-10-15
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.
摘要翻译： 本文公开了设计集成电路和集成电路块的模型的方法，电子设计自动化工具，装置和计算机可读介质。 在一个实施例中，设计集成电路的方法包括：（1）利用集成电路的设计者输入产生集成电路的定时预算，（2）使用定时预算为集成电路的块建立设计约束， （3）使用设计约束创建用于块的输入和输出定时预算，（4）将基于设计者知识的集成电路的实现信息与输入和输出定时预算组合以产生更新的输入和输出定时预算; 5）基于更新的输入和输出定时预算生成块的模型。
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8.发明授权Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics 失效系统基准系统和方法，用于标准化数据创建，分析和比较半导体技术节点特性公开(公告)号：US08307324B2
公开(公告)日：2012-11-06
申请号：US13212427
申请日：2011-08-18
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.
摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计用于时钟路径，数据路径和触发器路径的代表性基准电路，（2）建立用于代表性基准的延迟和功率的至少一个标准敏感度和测量规则 电路和技术节点的角落，（3）通过遍历角度范围进行扫描并以预定间隔跨越角落，（4）从模拟中提取数据，（5）将数据写入数据库和（ 6）解析和解释数据以产生至少一个报告。
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9.发明授权Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics 有权系统基准系统和方法，用于标准化数据创建，分析和比较半导体技术节点特性公开(公告)号：US08024694B2
公开(公告)日：2011-09-20
申请号：US12365084
申请日：2009-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G01R31/31725 , G06F1/04 , G06F1/26 , G06F1/3203 , G06F17/5081 , H03K19/215
摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing at least one representative benchmark circuit, (2) establishing standard sensitization and measurement rules for delay and power for the at least one representative benchmark circuit and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation and (5) parsing and interpreting the data to produce at least one report.
摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计至少一个代表性基准电路，（2）建立用于至少一个代表基准电路的延迟和功率的标准敏感度和测量规则，以及技术节点中的角部（3 ）通过遍历角度范围进行扫描并以预定间隔横跨角落执行模拟，（4）从模拟中提取数据，（5）解析和解释数据以产生至少一个报告。
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10.发明申请METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS 有权用于设计采用语境敏感和进步规则的集成电路的方法和使用方法之一的设备公开(公告)号：US20110022996A1
公开(公告)日：2011-01-27
申请号：US12510122
申请日：2009-07-27
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.
摘要翻译： 公开了设计IC和装置的方法。 在一个实施例中，一种方法包括：（1）创建用于IC设计的功能块的功能电路，（2）验证所述功能电路满足所述IC设计的规则集，其中所述规则集是基于上下文的 相对于所述设计流程，（3）基于功能电路合成逻辑电路; （4）验证逻辑电路满足规则集; （5）实现逻辑电路的物理布局; 和（6）验证物理布局满足规则集，其中该方法的每个步骤由至少一个EDA工具执行。
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