利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

31 条记录 (耗时 0.017 秒)

    SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY
    1.
    发明申请
    SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY 审中-公开
    用于分析和比较采用电压调节的集成电路和集成电路的优化方法的系统，正则化公制

    公开(公告)号：US20130055175A1

    公开(公告)日：2013-02-28

    申请号：US13599549

    申请日：2012-08-30

    申请人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    发明人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

    摘要： Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist.

    摘要翻译： 本文提供了设计集成电路（IC）的方法的各种实施例。 一种这样的方法的一个实施例包括：（1）产生功能IC设计，（2）确定功能IC设计的目标时钟速率，（3）从满足目标时钟速率的功能IC设计生成网表（ 4）从网表确定无单位性能/功率量化器，（5）尝试通过改变网表中的至少一些非关键路径中的速度，面积和功率消耗中的至少一个来增加无单位性能/功率量化器， 其中所述尝试由处理器执行，并且（6）从所述网表生成所述IC的布局。

    METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS
    2.
    发明申请
    METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CONTEXT-SENSITIVE AND PROGRESSIVE RULES AND AN APPARATUS EMPLOYING ONE OF THE METHODS 有权
    用于设计采用语境敏感和进步规则的集成电路的方法和使用方法之一的设备

    公开(公告)号：US20110022996A1

    公开(公告)日：2011-01-27

    申请号：US12510122

    申请日：2009-07-27

    申请人： James C. Parker ,  Vishwas M. Rao ,  Lalita M. Satapathy ,  Todd M. Tope

    发明人： James C. Parker ,  Vishwas M. Rao ,  Lalita M. Satapathy ,  Todd M. Tope

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： Methods of designing an IC and an apparatus are disclosed. In one embodiment, a method includes: (1) creating a functional circuit for a functional block of an IC design, (2) verifying said functional circuit satisfies a rule-set for said IC design, wherein said rule-set is context-based with respect to said design flow, (3) synthesizing a logical circuit based on the functional circuit; (4) verifying the logical circuit satisfies the rule set; (5) implementing a physical layout of the logical circuit; and (6) verifying the physical layout satisfies the rule set, wherein each step of the method is carried out by at least one EDA tool.

    摘要翻译： 公开了设计IC和装置的方法。 在一个实施例中，一种方法包括：（1）创建用于IC设计的功能块的功能电路，（2）验证所述功能电路满足所述IC设计的规则集，其中所述规则集是基于上下文的 相对于所述设计流程，（3）基于功能电路合成逻辑电路; （4）验证逻辑电路满足规则集; （5）实现逻辑电路的物理布局; 和（6）验证物理布局满足规则集，其中该方法的每个步骤由至少一个EDA工具执行。

    Method of emulating an ideal transformer valid from DC to infinite frequency
    4.
    发明授权
    Method of emulating an ideal transformer valid from DC to infinite frequency 失效
    从直流到无限频率仿真理想变压器的方法

    公开(公告)号：US06754616B1

    公开(公告)日：2004-06-22

    申请号：US09494821

    申请日：2000-01-31

    申请人： Bidyut K. Sen ,  James C. Parker ,  Richard L. Wheeler

    发明人： Bidyut K. Sen ,  James C. Parker ,  Richard L. Wheeler

    IPC分类号： G06G762

    CPC分类号： G06F17/5036 ,  H01F19/08

    摘要： A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.

    摘要翻译： 一种模拟理想变压器电气特性的方法。 理想变压器的表示是频率无关的，可用于模拟从直流到无限的频率范围内的理想变压器的性能。 在一个实施例中，理想变压器被表示为具有输入子电路和输出子电路。 每个子电路包括在电流控制的电流源上并联连接的电阻器。 输入电流，输出电流，电流源和电阻通过表示物理变压器的初级和次级绕组之间的匝数比的比例因子来缩放。 在本发明中，电流源负责电流缩放，电阻负责阻抗缩放。 该表示的电路元件可以用作生成用于电路仿真程序的一组输入参数的基础。

    Foreshortened log-periodic antenna employing inductively loaded and folded dipoles
    5.
    发明授权
    Foreshortened log-periodic antenna employing inductively loaded and folded dipoles 失效
    使用电感负载和折叠DIPOL的日常定向天线

    公开(公告)号：US3573839A

    公开(公告)日：1971-04-06

    申请号：US3573839D

    申请日：1969-04-24

    申请人： JAMES C PARKER JR

    发明人： PARKER JAMES C JR

    IPC分类号： H01Q11/10

    CPC分类号： H01Q11/10

    摘要： Some of the lower frequency elements of this planar dipole log periodic antenna are inductively loaded to reduce the size thereof and others of said lower frequency elements are both loaded and folded, and in addition the dipoles are provided with a mounting and supporting boom which also functions as a balanced low impedance transmission line.

    System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same
    6.
    发明授权
    System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the same 有权
    在多种情况下同时采用签约质量时序分析信息以减少电子电路中的动态功率的系统和方法及其结合的装置

    公开(公告)号：US08713506B2

    公开(公告)日：2014-04-29

    申请号：US13034167

    申请日：2011-02-24

    申请人： Bruce Zahn ,  James C. Parker ,  Benjamin Mbouombouo

    发明人： Bruce Zahn ,  James C. Parker ,  Benjamin Mbouombouo

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

    摘要： A dynamic power recovery system and method are disclosed herein. Additionally, an EDA tool and apparatus configured to perform dynamic power recovery are disclosed. In one embodiment, the system includes: (1) a power recovery module configured to carry out an instance of an initial power recovery process in each of multiple scenarios concurrently, the initial power recovery process including making first conditional downsizing of cells in at least one path in a circuit design with lower dynamic power cells and estimating a delay and a slack of the at least one path based on the first conditional downsizings and (2) a speed recovery module associated with the power recovery module and configured to carry out a speed recovery process in each of the multiple scenarios concurrently, the speed recovery process including determining whether the first conditional downsizings cause a timing violation with respect to the at least one path and making second conditional upsizings with higher dynamic power cells until the timing violation is removed.

    摘要翻译： 本文公开了动态功率恢复系统和方法。 此外，公开了一种被配置为执行动态功率恢复的EDA工具和装置。 在一个实施例中，系统包括：（1）功率恢复模块，被配置为在多个场景中同时执行初始功率恢复过程的一个实例，初始功率恢复过程包括在至少一个 在具有较低动态功率单元的电路设计中的路径，以及基于所述第一条件降序估计所述至少一个路径的延迟和松弛，以及（2）与所述功率恢复模块相关联的并且被配置为执行速度 所述速度恢复过程包括确定所述第一条件降序是否导致相对于所述至少一个路径的定时违反，并且使得具有较高动态功率单元的第二条件升高直到所述定时违反被去除。

    Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow
    7.
    发明授权
    Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow 失效
    分层设计中的时序收敛的建模方法利用设计流程的水平和垂直方面的分离

    公开(公告)号：US08341573B2

    公开(公告)日：2012-12-25

    申请号：US12905301

    申请日：2010-10-15

    申请人： Vishwas M. Rao ,  Joseph J. Jamann ,  James C. Parker

    发明人： Vishwas M. Rao ,  Joseph J. Jamann ,  James C. Parker

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

    摘要翻译： 本文公开了设计集成电路和集成电路块的模型的方法，电子设计自动化工具，装置和计算机可读介质。 在一个实施例中，设计集成电路的方法包括：（1）利用集成电路的设计者输入产生集成电路的定时预算，（2）使用定时预算为集成电路的块建立设计约束， （3）使用设计约束创建用于块的输入和输出定时预算，（4）将基于设计者知识的集成电路的实现信息与输入和输出定时预算组合以产生更新的输入和输出定时预算; 5）基于更新的输入和输出定时预算生成块的模型。

    Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics
    8.
    发明授权
    Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics 失效
    系统基准系统和方法，用于标准化数据创建，分析和比较半导体技术节点特性

    公开(公告)号：US08307324B2

    公开(公告)日：2012-11-06

    申请号：US13212427

    申请日：2011-08-18

    申请人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    发明人： Joseph J. Jamann ,  James C. Parker ,  Vishwas M. Rao

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G01R31/31725 ,  G06F1/04 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5081 ,  H03K19/215

    摘要： One aspect provides a method of standardized data creation and analysis of semiconductor technology node characteristics. In one embodiment, the method includes: (1) designing representative benchmark circuits for a clock path, a data path and a flip-flop path, (2) establishing at least one standard sensitization and measurement rule for delay and power for the representative benchmark circuits and across corners in the technology nodes, (3) performing a simulation by sweeping through a range of values and at predetermined intervals across the corners, (4) extracting data from the simulation, (5) writing the data to a databank and (6) parsing and interpreting the data to produce at least one report.

    摘要翻译： 一方面提供了半导体技术节点特性的标准化数据创建和分析方法。 在一个实施例中，该方法包括：（1）设计用于时钟路径，数据路径和触发器路径的代表性基准电路，（2）建立用于代表性基准的延迟和功率的至少一个标准敏感度和测量规则 电路和技术节点的角落，（3）通过遍历角度范围进行扫描并以预定间隔跨越角落，（4）从模拟中提取数据，（5）将数据写入数据库和（ 6）解析和解释数据以产生至少一个报告。

    METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
    9.
    发明申请
    METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD 失效
    设计采用分层分层设计流程的集成电路的方法和采用该方法的设备

    公开(公告)号：US20120174048A1

    公开(公告)日：2012-07-05

    申请号：US13421710

    申请日：2012-03-15

    申请人： Vishwas M. Rao ,  James C. Parker

    发明人： Vishwas M. Rao ,  James C. Parker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5045 ,  G06F2217/84

    摘要： Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.

    摘要翻译： 公开了设计IC和分层设计流发生器的方法。 在一个实施例中，该方法包括：（1）在设备处接收用于IC设计的定时和物理约束，（2）建立分层设计流程，以提供采用该设备的IC设计的实现，以及（3） 设计流入后期设计流程部分和采用该装置的早期设计流程部分，其中后期设计流程部分对于不同的设计流程方法基本相同。

    METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS
    10.
    发明申请
    METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING PRE-DETERMINED TIMING-REALIZABLE CLOCK-INSERTION DELAYS AND INTEGRATED CIRCUIT DESIGN TOOLS 有权
    设计采用预先确定的时序实时时钟延迟和集成电路设计工具的集成电路的方法

    公开(公告)号：US20120011484A1

    公开(公告)日：2012-01-12

    申请号：US12831038

    申请日：2010-07-06

    申请人： Vishwas M. Rao ,  James C. Parker

    发明人： Vishwas M. Rao ,  James C. Parker

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/62

    摘要： A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.

    摘要翻译： 本文公开了一种设计集成电路，EDA工具，装置和计算机可读介质的方法。 在一个实施例中，该方法包括：（1）生成表示集成电路的时钟插入延迟值的一组约束方程作为变量，（2）基于约束方程确定每个时钟插入延迟值的边界;以及 （3）基于用于驱动所述集成电路的设计以关闭的边界产生一组关闭命令，其中所述方法的每个步骤由至少一个EDA工具执行。