公开(公告)号：US20110198721A1

公开(公告)日：2011-08-18

申请号：US12704695

申请日：2010-02-12

申请人： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

发明人： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC分类号： H01L23/544 ,  H01L21/304 ,  H01L21/306 ,  H01L29/06 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L2224/02372

摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

摘要翻译： 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

公开(公告)号：US20050170980A1

公开(公告)日：2005-08-04

申请号：US10769245

申请日：2004-01-30

申请人： Hsin-Hsien Lu ,  Han-Hsin Kuo ,  Ying-Ho Chen ,  Syum-Ming Jang

发明人： Hsin-Hsien Lu ,  Han-Hsin Kuo ,  Ying-Ho Chen ,  Syum-Ming Jang

IPC分类号： C11D7/26 ,  C11D11/00 ,  H01L21/02 ,  C11D1/00

CPC分类号： C11D7/262 ,  C11D7/261 ,  C11D11/0047 ,  H01L21/02074

摘要： A method for the cleaning of wafers typically during a chemical mechanical polishing (CMP) process. The method includes polishing a material layer on a wafer in sequential polishing steps, rinsing the wafer using a novel surfactant composition solution after at least one of the polishing steps and rinsing of the wafer using deionized water, respectively. The surfactant composition solution imparts a generally hydrophilic character to a hydrophobic material layer such as a high-k dielectric layer on the wafer. Consequently, the layer is rendered amenable to cleaning by deionized water, thereby significantly enhancing the removal of particles from the layer and reducing the number of defects related to the CMP process.

摘要翻译： 通常在化学机械抛光（CMP）工艺期间清洗晶片的方法。 该方法包括在顺序抛光步骤中抛光晶片上的材料层，在至少一个抛光步骤和使用去离子水冲洗晶片之后，使用新型表面活性剂组合物溶液冲洗晶片。 表面活性剂组合物溶液对疏水性材料层（例如晶片上的高k电介质层）具有普遍的亲水性。 因此，该层适于用去离子水清洗，从而显着增强颗粒从层中的去除并减少与CMP工艺相关的缺陷数量。

公开(公告)号：US06677251B1

公开(公告)日：2004-01-13

申请号：US10207339

申请日：2002-07-29

申请人： Hsin-Hsien Lu ,  Aaron Song ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Hsin-Hsien Lu ,  Aaron Song ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2131

CPC分类号： H01L21/76826 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814

摘要： A method for forming a dielectric insulating layer with increased hydrophilicity for improving adhesion of an adjacently deposited material layer in semiconductor device manufacturing including providing a semiconductor wafer having a process surface for forming a dielectric insulting layer thereover; depositing the dielectric insulating layer; and, subjecting the dielectric insulating layer including an exposed surface to a hydrophilicity increasing treatment including at least one of a dry plasma treatment and a wet process including contacting the exposed surface with a hydrophilicity increasing solution including a surfactant said wet process followed by a baking process to improve an adhesion of an adjacently deposited material layer.

摘要翻译： 一种用于形成具有增加的亲水性以提高相邻沉积材料层在半导体器件制造中的粘合性的介电绝缘层的方法，包括提供具有用于在其上形成介电绝缘层的工艺表面的半导体晶片; 沉积介电绝缘层; 并且使包含暴露表面的介电绝缘层经受包括干法等离子处理和湿法中的至少一种的亲水性增加处理，包括使暴露表面与包含表面活性剂的亲水性增加溶液接触，然后进行烘烤处理 以改善相邻沉积材料层的粘附性。

公开(公告)号：US06770570B2

公开(公告)日：2004-08-03

申请号：US10295609

申请日：2002-11-15

申请人： Lih-Ping Li ,  Hsin-Hsien Lu ,  Syun-Ming Jang

发明人： Lih-Ping Li ,  Hsin-Hsien Lu ,  Syun-Ming Jang

IPC分类号： H01L21469

CPC分类号： H01L21/76828 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76835

摘要： A semiconductor device 100 includes a low-k dielectric insulator 104. In the preferred embodiment, a low-k dielectric material 104 is deposited. This material 104 is then cured using a plasma cure step. The cure process causes the density of the top portion 106 of layer 104 to be increased. The higher density portion 106, however, also has a higher dielectric constant. As a result, the dielectric constant of the layer 104 can be reduced by removing this higher density portion 106. This leads to a lower dielectric constant (e.g., less than about 3) of the bulk film.

摘要翻译： 半导体器件100包括低k电介质绝缘体104.在优选实施例中，沉积低k电介质材料104。 然后使用等离子体固化步骤固化该材料104。 固化过程使得层104的顶部106的密度增加。 然而，较高密度部分106也具有较高的介电常数。 结果，可以通过去除该较高密度部分106来降低层104的介电常数。这导致本体膜的较低的介电常数（例如小于约3）。