公开(公告)号：US08252682B2

公开(公告)日：2012-08-28

申请号：US12704695

申请日：2010-02-12

申请人： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

发明人： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L2224/02372

摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

摘要翻译： 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

公开(公告)号：US20110198721A1

公开(公告)日：2011-08-18

申请号：US12704695

申请日：2010-02-12

申请人： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

发明人： Ku-Feng YANG ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC分类号： H01L23/544 ,  H01L21/304 ,  H01L21/306 ,  H01L29/06 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L2224/02372

摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

摘要翻译： 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

公开(公告)号：US20050070058A1

公开(公告)日：2005-03-31

申请号：US10672769

申请日：2003-09-26

申请人： Han-Ti Hsiaw ,  Shwang-Ming Jeng ,  Shih-Ming Wang ,  Fu-Chi Hsu

发明人： Han-Ti Hsiaw ,  Shwang-Ming Jeng ,  Shih-Ming Wang ,  Fu-Chi Hsu

IPC分类号： H01L21/3105 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823871

摘要： An ILD dielectric layer stack and method for forming the same, the method includes a semiconductor substrate including CMOS transistors with gate electrode portions; depositing a first layer including phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and forming metal filled local interconnects extending through a thickness portion of the first and second layers.

摘要翻译： 一种ILD介电层堆叠及其形成方法，该方法包括：具有栅电极部分的CMOS晶体管的半导体衬底; 在所述半导体衬底上沉积包括磷掺杂SiO 2的第一层至足以覆盖包括中间间隙的栅电极部分的厚度; 在随后的氧化物化学机械抛光（CMP）平坦化工艺之后，将第二层未掺杂SiO 2沉积在第一层上并接触第一层至足以使第二层厚度部分覆盖第一层的厚度; 执行氧化物CMP工艺以使第二层平坦化并离开第二层厚度部分; 以及形成延伸穿过所述第一和第二层的厚度部分的金属填充的局部互连。

公开(公告)号：US06869836B1

公开(公告)日：2005-03-22

申请号：US10672769

申请日：2003-09-26

申请人： Han-Ti Hsiaw ,  Shwang-Ming Jeng ,  Shih-Ming Wang ,  Fu-Chi Hsu

发明人： Han-Ti Hsiaw ,  Shwang-Ming Jeng ,  Shih-Ming Wang ,  Fu-Chi Hsu

IPC分类号： H01L21/3105 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823871

摘要： An ILD dielectric layer stack and method for forming the same, the method includes a semiconductor substrate including CMOS transistors with gate electrode portions; depositing a first layer including phosphorous doped SiO2 over the semiconductor substrate to a thickness sufficient to cover the gate electrode portions including intervening gaps; depositing a second layer of undoped SiO2 over and contacting the first layer to a thickness sufficient to leave a second layer thickness portion overlying the first layer following a subsequent oxide chemical mechanical polish (CMP) planarization process; carrying out the oxide CMP process to planarize the second layer and leave the second layer thickness portion; and forming metal filled local interconnects extending through a thickness portion of the first and second layers.

摘要翻译： 一种ILD介电层堆叠及其形成方法，该方法包括：具有栅电极部分的CMOS晶体管的半导体衬底; 在所述半导体衬底上沉积包括磷掺杂SiO 2的第一层至足以覆盖包括中间间隙的栅电极部分的厚度; 在随后的氧化物化学机械抛光（CMP）平坦化工艺之后，将第二层未掺杂SiO 2沉积在第一层上并接触第一层至足以使第二层厚度部分覆盖第一层的厚度; 执行氧化物CMP工艺以使第二层平坦化并离开第二层厚度部分; 以及形成延伸穿过所述第一和第二层的厚度部分的金属填充的局部互连。