公开(公告)号：US06261912B1

公开(公告)日：2001-07-17

申请号：US09372432

申请日：1999-08-10

申请人： Chih-Yuan Hsiao ,  Yao-Chin Cheng

发明人： Chih-Yuan Hsiao ,  Yao-Chin Cheng

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/665 ,  H01L29/6659

摘要： A method of fabricating a transistor. A gate structure is formed on a substrate. A spacer is formed on a sidewall of the gate structure. A first doping step is performed with the gate structure and the spacer serving as masks to form a source/drain region in the substrate. A silicide layer is formed on the source/drain region. The spacer is removed. A second doping step is performed with the gate structure serving as a mask to form a lightly doped drain region in the substrate.

摘要翻译： 一种制造晶体管的方法。 在基板上形成栅极结构。 在栅极结构的侧壁上形成间隔物。 利用栅极结构和间隔物用作掩模来执行第一掺杂步骤，以在衬底中形成源极/漏极区域。 在源极/漏极区域上形成硅化物层。 移除间隔物。 执行第二掺杂步骤，栅极结构用作掩模，以在衬底中形成轻掺杂漏极区。

公开(公告)号：US06646310B2

公开(公告)日：2003-11-11

申请号：US09915930

申请日：2001-07-26

申请人： Chih-Yuan Hsiao ,  Po-Jau Tsao

发明人： Chih-Yuan Hsiao ,  Po-Jau Tsao

IPC分类号： H01L29772

CPC分类号： H01L27/11 ,  G11C11/412

摘要： A four-transistor SRAM cell, which could be viewed as at least including two word line terminals, comprises the following elements: a first word line terminal, a second word line terminal, a first bit line terminal, a second bit line terminal, a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate of the first transistor is coupled to the first word line terminal and the source of the first transistor is coupled to the first bit line terminal, the gate of the second transistor is coupled to the second word line terminal and the source of the second transistor is coupled to the second bit line terminal, the source of the third transistor is coupled to the drain of the first transistor and the gate of the third transistor is coupled to the drain of the second transistor, the source of the fourth transistor is coupled to the drain of the second transistor and the gate of the fourth transistor is coupled to the drain of the first transistor. Significantly, one essential characteristic of the memory cell is that two word line terminals are used to control the state of two independent transistors separately.

摘要翻译： 可以看作至少包括两个字线端子的四晶体管SRAM单元包括以下元件：第一字线端子，第二字线端子，第一位线端子，第二位线端子，第二位线端子 第一晶体管，第二晶体管，第三晶体管和第四晶体管。 第一晶体管的栅极耦合到第一字线端子，第一晶体管的源极耦合到第一位线端子，第二晶体管的栅极耦合到第二字线端子，第二晶体管的源极与第二晶体管的源极耦合， 晶体管耦合到第二位线端子，第三晶体管的源极耦合到第一晶体管的漏极，并且第三晶体管的栅极耦合到第二晶体管的漏极，第四晶体管的源极耦合 到第二晶体管的漏极，并且第四晶体管的栅极耦合到第一晶体管的漏极。 重要的是，存储单元的一个基本特征是两个字线端子分别用于控制两个独立晶体管的状态。

公开(公告)号：US5946574A

公开(公告)日：1999-08-31

申请号：US218540

申请日：1998-12-22

申请人： Chih-Yuan Hsiao

发明人： Chih-Yuan Hsiao

IPC分类号： H01L21/8234 ,  H01L27/02

CPC分类号： H01L21/8234 ,  H01L27/0255

摘要： A method for forming a protection circuit that starts with forming a first-type well and a second-type well on a first-type substrate. By forming isolations, a first active region is defined within the second-type well, and a second active region, a third active region and a fourth active region are defined within the first-type well. A first polysilicon layer is formed on the substrate and patterned to expose the third and the fourth active regions. A second polysilicon layer is formed on the substrate and patterned into a first gate that connects the first and the third active regions, and a second gate that connects the second and the fourth active regions. Then, by performing a first-type implantation process, the first gate is turned into a first-type gate. First-type source/drain regions are formed in the first active region, and first-type contacts are formed in the third active region as well. Similarly, the second gate is turned into a second-type gate, second-type source/drain regions are formed in the second active region, and second-type contacts are formed in the fourth active region by performing a second-type implantation process.

摘要翻译： 一种用于形成保护电路的方法，该保护电路从在第一类型基片上形成第一类型阱和第二类型阱开始。 通过形成隔离，第一有源区被限定在第二类阱内，第一有源区，第三有源区和第四有源区被限定在第一类阱内。 第一多晶硅层形成在衬底上并被图案化以暴露第三和第四有源区。 第二多晶硅层形成在衬底上并被图案化成连接第一和第三有源区的第一栅极和连接第二和第四有源区的第二栅极。 然后，通过进行第一种注入工艺，将第一栅极变成第一型栅极。 第一类型源极/漏极区域形成在第一有源区中，并且第一类型接触也形成在第三有源区中。 类似地，第二栅极变成第二类栅极，第二类型源极/漏极区形成在第二有源区中，并且通过执行第二类型注入工艺在第四有源区中形成第二类型的接触。

公开(公告)号：US20050168740A1

公开(公告)日：2005-08-04

申请号：US11090643

申请日：2005-03-25

申请人： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

发明人： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

IPC分类号： G03F7/20 ,  G03F9/00 ,  G01B11/00 ,  G06F17/50

CPC分类号： G03F9/7019 ,  G03F7/70633 ,  G03F9/7011

摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.

摘要翻译： 一种用于评估两个掩模版图案之间的掩模版配准的方法。 通过用其上具有第一掩模版图案的第一掩模版通过光刻来限定和蚀刻晶片以形成第一曝光图案。 在晶片上形成光致抗蚀剂层，并通过光刻法将其定义为第二曝光图案，其上具有第二掩模版图案的第二掩模版。 通过CD-SEM测量第一和第二曝光图案之间的偏差值。 根据缩放程度和覆盖偏移校正偏差值，以获得注册数据。 基于登记数据评价两个掩模图案之间的掩模版登记。

公开(公告)号：US06686635B2

公开(公告)日：2004-02-03

申请号：US10033786

申请日：2002-01-03

申请人： Chih-Yuan Hsiao

发明人： Chih-Yuan Hsiao

IPC分类号： H01L2976

CPC分类号： H01L27/11

摘要： A method for forming transistors static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell area and periphery area, wherein the cell area comprises a first P-type region, a second P-type region, a first N-type region and a second N-type region, the periphery area comprises numerous periphery P-type regions and numerous periphery N-type regions; covering the first P-type region, the second P-type region and the periphery P-type regions by a first photoresist; forming numerous N-type sources and numerous N-type drains in the first P-type region, the second P-type region and the periphery P-type regions. Remove the first photoresist. Use a second photoresist to cover the periphery N-type regions and some the N-type drains which are located in both the first N-type region and the second N-type regions; and performing a large angle implanting process to form numerous P-type enlarged drains and numerous P-type region and the P-type second region, wherein numerous P-type extra sources also are formed on outside of some the N-type drains which are located in both the first N-type region and the second N-type region.

摘要翻译： 一种用于形成晶体管静态随机存取存储器的方法。 该方法包括以下步骤：提供至少包括单元区域和外围区域的基板，其中单元区域包括第一P型区域，第二P型区域，第一N型区域和第二N型区域 周边区域包括多个周边P型区域和许多外围N型区域; 通过第一光致抗蚀剂覆盖第一P型区域，第二P型区域和周边P型区域; 在第一P型区域，第二P型区域和周边P型区域中形成多个N型源极和多个N型漏极。 去除第一个光刻胶。 使用第二光致抗蚀剂覆盖位于第一N型区域和第二N型区域中的周边N型区域和一些N型漏极; 并且进行大角度注入工艺以形成多个P型放大漏斗和多个P型区域和P型第二区域，其中在一些N型排水管的外侧还形成许多P型额外源， 位于第一N型区域和第二N型区域中。

公开(公告)号：US06366493B1

公开(公告)日：2002-04-02

申请号：US09695161

申请日：2000-10-24

申请人： Chih-Yuan Hsiao ,  Po-Jau Tsao

发明人： Chih-Yuan Hsiao ,  Po-Jau Tsao

IPC分类号： G11C1100

CPC分类号： H01L27/11 ,  G11C11/412

摘要： A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor. Significantly, one essentially characteristic of the memory cell is two word line terminals are used to control state of two independent transistors separately.

摘要翻译： 可以看作至少包括两个字线端子的四晶体管SRAM单元包括以下元件：第一字线端子，第二字线端子，第一位线端子，第二位线端子，第一晶体管，第二晶体管， 第三晶体管和第四晶体管。 由此，第一晶体管的栅极耦合到第一字线端子，第一晶体管的源极耦合到第一位线端子，第二晶体管的栅极耦合到第二字线端子，第二晶体管的源极耦合到第二位线端子 第三晶体管的源极耦合到第一晶体管的漏极，第三晶体管的栅极耦合到第二晶体管的漏极，第四晶体管的源极耦合到第二晶体管的漏极，第四晶体管的栅极耦合到第一晶体管的漏极。 显着地，存储器单元的一个基本特征是两个字线端子分别用于控制两个独立晶体管的状态。

公开(公告)号：US06238988B1

公开(公告)日：2001-05-29

申请号：US09457137

申请日：1999-12-09

申请人： Chih-Yuan Hsiao ,  Hua-Chou Tseng

发明人： Chih-Yuan Hsiao ,  Hua-Chou Tseng

IPC分类号： H01L21336

CPC分类号： H01L29/0847 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

摘要： The present invention relates to a method of forming a MOS transistor on a semiconductor wafer. A gate is first formed on the silicon substrate of the semiconductor wafer, then a first spacer made of silicon nitride and the LDD are formed adjacent to the gate. A conductive layer is formed on the semiconductor wafer that forms a corner on the conjoining section of the spacer and the silicon substrate. A spacer made of silicon oxide is formed on the corner of the conductive layer 58, then an etching process is performed to remove the conductive layer above the gate and the silicon substrate. The conductive layer on the corner adjacent to the first spacer remains. Finally, the spacer made of silicon oxide is completely removed, and an ion implantation process is performed to form a source and drain on the silicon substrate adjacent to the conductive layer.

摘要翻译： 本发明涉及在半导体晶片上形成MOS晶体管的方法。 首先在半导体晶片的硅衬底上形成栅极，然后在栅极附近形成由氮化硅制成的第一间隔物和LDD。 导电层形成在半导体晶片上，该半导体晶片在间隔物和硅衬底的结合部分上形成角部。 在导电层58的角部形成由氧化硅构成的间隔物，然后进行蚀刻处理，以除去栅极和硅衬底之上的导电层。 与第一间隔物相邻的角部上的导电层残留。 最后，完全除去由氧化硅制成的间隔物，并且在邻近导电层的硅衬底上进行离子注入工艺以形成源极和漏极。

公开(公告)号：US06174776B1

公开(公告)日：2001-01-16

申请号：US09425604

申请日：1999-10-22

申请人： Ching-Chiao Hao ,  Chih-Yuan Hsiao ,  Hua-Chou Tseng

发明人： Ching-Chiao Hao ,  Chih-Yuan Hsiao ,  Hua-Chou Tseng

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/665 ,  H01L29/66659

摘要： A method for forming a gate contact is disclosed. The method includes that a semiconductor substrate and a silicon dioxide layer are provided upon the semiconductor substrate. Then, a polysilicon layer is formed upon the oxide layer. Next, defining and etching the polysilicon layer are carried out to form a gate. Implanting upon the top surface of the silicon dioxide layer is achieved so that source/drain region is formed below and abuts the silicon dioxide layer. The source/drain region will be annealed. A spacer can be formed and abuts the sidewall of the gate. A salicide is formed and overlaps the top surface of the gate and over the semiconductor substrate. Then, a gate contact area can be defined upon the top surface of the semiconductor substrate by using a mask that has a pattern covering approximately half of the gate and the spacer. The half of the spacer can be removed without covering by the mask. Finally, implanting will be completed to form the gate contact in the substrate by using the salicide as an implanting mask.

摘要翻译： 公开了一种用于形成栅极接触的方法。 该方法包括在半导体衬底上设置半导体衬底和二氧化硅层。 然后，在氧化物层上形成多晶硅层。 接下来，进行多晶硅层的定义和蚀刻以形成栅极。 实现了植入到二氧化硅层的顶表面上，使得源/漏区形成在下方并与二氧化硅层相邻。 源极/漏极区域将被退火。 间隔件可以形成并邻接门的侧壁。 形成硅化物并与栅极的顶表面和半导体衬底上方重叠。 然后，通过使用具有覆盖栅极和间隔物的大约一半的图案的掩模，可以在半导体衬底的顶表面上限定栅极接触区域。 间隔物的一半可以被去除而不被掩模覆盖。 最后，通过使用自对准硅胶作为植入掩模，完成注入以在基板中形成栅极接触。