公开(公告)号：US20090233448A1

公开(公告)日：2009-09-17

申请号：US12119275

申请日：2008-05-12

Applicant: Kuo-Yao CHO ,  Wen-Bin WU ,  Ya-Chih WANG ,  Chiang-Lin SHIH ,  Chao-Wen LAY ,  Chih-Huang WU

Inventor： Kuo-Yao CHO ,  Wen-Bin WU ,  Ya-Chih WANG ,  Chiang-Lin SHIH ,  Chao-Wen LAY ,  Chih-Huang WU

IPC: H01L21/306

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.

Abstract translation: 一种改善半导体上的光刻分辨率的方法，包括提供其上依次形成保护层，第一蚀刻层和光致抗蚀剂层的基板的步骤; 图案化光致抗蚀剂层以形成开口，以便部分地露出第一蚀刻层; 将第一离子注入到所揭示的第一蚀刻层中以形成第一掺杂区域; 以及将第二离子注入到所揭示的第一蚀刻层中以形成第二掺杂区域，其中所述第一掺杂区域与所述第二掺杂区域无关。

公开(公告)号：US20070190736A1

公开(公告)日：2007-08-16

申请号：US11616849

申请日：2006-12-27

Applicant: An-Hsiung Liu ,  Chiang-Lin Shih ,  Wen-Bin Wu ,  Hui-Min Mao ,  Lin-Chin Su ,  Pei-Ing Lee

Inventor： An-Hsiung Liu ,  Chiang-Lin Shih ,  Wen-Bin Wu ,  Hui-Min Mao ,  Lin-Chin Su ,  Pei-Ing Lee

IPC: H01L21/20

CPC classification number: H01L29/66181 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L27/1087 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A small-size (w

Abstract translation: 提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。 利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

公开(公告)号：US06998226B2

公开(公告)日：2006-02-14

申请号：US10193464

申请日：2002-07-10

Applicant: Yuan-Hsun Wu ,  Wen-Bin Wu ,  Yung Long Hung ,  Ya Chih Wang

Inventor： Yuan-Hsun Wu ,  Wen-Bin Wu ,  Yung Long Hung ,  Ya Chih Wang

IPC: G03F7/38 ,  G03F7/40

CPC classification number: G03F7/168 ,  G03F7/091 ,  G03F7/2022 ,  G03F7/38 ,  Y10S430/151

Abstract: A method of forming a patterned photoresist layer. First, an anti-reflection coating layer is formed on a substrate. Next, a first bake is performed. A photoresist layer is then formed on the anti-reflection coating layer. Exposure is performed. A second bake is performed, wherein the temperature difference between the first bake and the second bake is about 35 ° C.˜55 ° C. Finally, development is performed. The patterned photoresist layer features have perfect profiles in accordance with this invention.

Abstract translation: 形成图案化光致抗蚀剂层的方法。 首先，在基板上形成防反射涂层。 接下来，进行第一烘焙。 然后在抗反射涂层上形成光致抗蚀剂层。 曝光进行。 进行第二烘烤，其中第一烘烤和第二烘烤之间的温度差为约35℃〜55℃。最后，进行显影。 图案化的光致抗蚀剂层特征具有根据本发明的完美的轮廓。

公开(公告)号：US20050127356A1

公开(公告)日：2005-06-16

申请号：US10732370

申请日：2003-12-11

Applicant: Wen-Bin Wu

Inventor： Wen-Bin Wu

IPC: G03F1/14 ,  H01L21/66 ,  H01L23/58 ,  H01L29/10

CPC classification number: H01L22/12 ,  G03F1/44 ,  G03F7/70625

Abstract: Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test mask pattern region having a second pattern density. In the test mask structure of the present invention, the required pattern density is obtained by adjusting the area of the array pattern region and the area of the test mask pattern region according to the first pattern density and the second pattern density.

Abstract translation: 公开了一种测试掩模结构。 本发明的测试掩模结构至少包括与最终产品一定比例的阵列图案区域，其具有按照一定比例的第一图案密度; 以及具有第二图案密度的至少一个测试掩模图案区域。 在本发明的测试掩模结构中，通过根据第一图案密度和第二图案密度调整阵列图案区域的面积和测试掩模图案区域的面积来获得所需的图案密度。

公开(公告)号：US6145358A

公开(公告)日：2000-11-14

申请号：US291287

申请日：1999-04-14

Applicant: Wen-Bin Wu

Inventor： Wen-Bin Wu

IPC: E05B13/00 ,  E05B15/00 ,  E05B15/02 ,  E05B55/04

CPC classification number: E05B13/004 ,  E05B15/02 ,  E05B15/0053 ,  Y10T70/5394 ,  Y10T70/7723 ,  Y10T70/7915

Abstract: An auxiliary lock includes an exterior lock assembly having a knob and an actuating plate that is connected to the knob to rotate therewith. A casing is mounted inside a door for rotatably supporting a knob that is also connected to the actuating plate to rotate therewith. A control plate is mounted in the casing and includes a first end extended beyond the casing for manual operation. A second end of the control plate includes a notch releasably engaged with one of a number of teeth of an engaging wheel mounted in the casing. The control plate is movable vertically and retained in place by a positioning element. The engaging wheel is connected to the actuating plate to rotate therewith.

Abstract translation: 辅助锁包括具有旋钮的外部锁定组件和连接到旋钮以随之旋转的致动板。 壳体安装在门内，用于可旋转地支撑旋钮，该旋钮也连接到致动板以与其一起旋转。 控制板安装在壳体中，并且包括延伸超出壳体的用于手动操作的第一端。 控制板的第二端包括可拆卸地与安装在壳体中的接合轮的多个齿中的一个啮合的凹口。 控制板可以垂直移动并通过定位元件保持在适当位置。 接合轮连接到致动板以与其一起旋转。

公开(公告)号：US08399891B2

公开(公告)日：2013-03-19

申请号：US12943933

申请日：2010-11-11

Applicant: Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

Inventor： Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

IPC: H01L29/72

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 在衬底上形成包括分离的扫描线图案的第一图案化导电层。 每个扫描线图案包括彼此相邻的第一和第二扫描线。 第一和第二扫描线都具有第一和第二触点。 执行对扫描线图案的公开检查。 沟道层形成在衬底上。 包括与第一和第二扫描线隔开的数据线，位于沟道层上方的源极和漏极以及连接器的第二图案化导电层形成在衬底上。 电源相应地电连接数据线。 至少一个连接器电连接第一和第二扫描线，以便在每个扫描线图案中形成环。 形成与漏极电连接的像素电极。

公开(公告)号：US20120043558A1

公开(公告)日：2012-02-23

申请号：US12943933

申请日：2010-11-11

Applicant: Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

Inventor： Po-Lin Lai ,  Ying-Fa Huang ,  Chun-Ming Yang ,  Wen-Bin Wu ,  Wen-Yi Lin

IPC: H01L27/15 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: An active device array substrate and a fabricating method thereof are provided. A first patterned conductive layer including separated scan line patterns is formed on a substrate. Each scan line pattern includes a first and second scan lines adjacent to each other. Both the first and the second scan lines have first and second contacts. An open inspection on the scan line patterns is performed. Channel layers are formed on the substrate. A second patterned conductive layer including data lines interlaced with the first and second scan lines, sources and drains located above the channel layers, and connectors is formed on the substrate. The sources electrically connect the data lines correspondingly. At least one of the connectors electrically connects the first and second scan lines, so as to form a loop in each scan line pattern. Pixel electrodes electrically connected to the drains are formed.

Abstract translation: 提供一种有源器件阵列衬底及其制造方法。 在衬底上形成包括分离的扫描线图案的第一图案化导电层。 每个扫描线图案包括彼此相邻的第一和第二扫描线。 第一和第二扫描线都具有第一和第二触点。 执行对扫描线图案的公开检查。 沟道层形成在衬底上。 包括与第一和第二扫描线隔开的数据线，位于沟道层上方的源极和漏极以及连接器的第二图案化导电层形成在衬底上。 电源相应地电连接数据线。 至少一个连接器电连接第一和第二扫描线，以便在每个扫描线图案中形成环。 形成与漏极电连接的像素电极。

公开(公告)号：US20080251933A1

公开(公告)日：2008-10-16

申请号：US11845746

申请日：2007-08-27

Applicant: Kuo-Yao Cho ,  Wen-Bin Wu ,  Chiang-Lin Shih ,  Chia-Cheng Lin

Inventor： Kuo-Yao Cho ,  Wen-Bin Wu ,  Chiang-Lin Shih ,  Chia-Cheng Lin

IPC: H01L23/525 ,  H01L23/52

CPC classification number: H01L23/528 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction.

Abstract translation: 金属互连结构包括彼此相邻的多个第一插塞，第一金属线在第一方向上延伸并接触每个第一插塞以形成第一部分，第一部分之间具有锥形第二部分，第二插头与第二插头相邻 在第一方向垂直的第二方向上。

公开(公告)号：US20080032205A1

公开(公告)日：2008-02-07

申请号：US11513288

申请日：2006-08-31

Applicant: Chui-fu Chiu ,  Wen-Bin Wu

Inventor： Chui-fu Chiu ,  Wen-Bin Wu

IPC: G03F1/00 ,  G03F9/00 ,  G03C5/00 ,  H01L23/544

CPC classification number: G03F7/70633

Abstract: An overlay mark formed on a photomask, comprising a first rectangular region, a second rectangular region, a third rectangular region, and a fourth rectangular region, each rectangular region having the same pattern configuration, a longer side of the first rectangular region and a longer side of the third rectangular region being parallel to each other, and a longer side of the second rectangular region and a longer side of the fourth rectangular region being parallel to each other, the longer side of the first rectangular region being perpendicular to the longer side of the second rectangular region; wherein each pattern configuration has at least two different pattern elements allowing other pattern elements be chosen to align when any one of the pattern elements on the substrate was damaged during process.

Abstract translation: 形成在光掩模上的覆盖标记，包括第一矩形区域，第二矩形区域，第三矩形区域和第四矩形区域，每个矩形区域具有相同的图案构造，第一矩形区域的长边和较长的 所述第三矩形区域的一侧彼此平行，并且所述第二矩形区域的长边和所述第四矩形区域的长边彼此平行，所述第一矩形区域的长边垂直于所述长边 的第二矩形区域; 其中每个图案配置具有至少两个不同的图案元件，当在处理期间衬底上的任何一个图案元件被损坏时，允许其它图案元件被选择以对准。

公开(公告)号：US07304323B2

公开(公告)日：2007-12-04

申请号：US10732370

申请日：2003-12-11

Applicant: Wen-Bin Wu

Inventor： Wen-Bin Wu

IPC: H01L23/58 ,  H01L29/10

CPC classification number: H01L22/12 ,  G03F1/44 ,  G03F7/70625

Abstract: Disclosed is a test mask structure. The test mask structure of the present invention comprises at least an array pattern region, in a certain proportion to the final product, having a first pattern density according to the certain proportion; and at least one test mask pattern region having a second pattern density. In the test mask structure of the present invention, the required pattern density is obtained by adjusting the area of the array pattern region and the area of the test mask pattern region according to the first pattern density and the second pattern density.

Abstract translation: 公开了一种测试掩模结构。 本发明的测试掩模结构至少包括与最终产品一定比例的阵列图案区域，其具有按照一定比例的第一图案密度; 以及具有第二图案密度的至少一个测试掩模图案区域。 在本发明的测试掩模结构中，通过根据第一图案密度和第二图案密度调整阵列图案区域的面积和测试掩模图案区域的面积来获得所需的图案密度。