公开(公告)号：US20100049876A1

公开(公告)日：2010-02-25

申请号：US12612078

申请日：2009-11-04

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F15/16

CPC classification number: H04L63/10 ,  H04L47/50 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9063

Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

Abstract translation: 大体上描述了一种从计算设备接收数据包以便传输到网络上的网络接口设备，具有一定特性的数据分组仅在发送队列具有发送具有该特性的分组的权限时发送分组。 数据包特征可以包括传输协议号，源和目的端口号，源和目的IP地址。 基于建立队列的进程的权限级别，可以通过内核例程在建立传输队列时将授权编程到NIC中。 以这种方式，用户进程可以使用不受信任的用户级协议栈来发起到网络上的数据传输，而NIC保护系统或网络的其余部分免受某些种类的折中。

公开(公告)号：US20070174511A1

公开(公告)日：2007-07-26

申请号：US11329444

申请日：2006-01-11

Applicant: Ching Yu ,  David Riddoch ,  Steve Pope ,  John Chiang ,  Alok Singh ,  Derek Roberts

Inventor： Ching Yu ,  David Riddoch ,  Steve Pope ,  John Chiang ,  Alok Singh ,  Derek Roberts

IPC: G06F3/00

CPC classification number: G06F13/28

Abstract: System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace engine includes a binning controller for receiving queues from a transmit DMA queue manager and determines the earliest allowed time for a particular queue that is stored and paced in a Work Bin, a Fast Bin, or a Slow Bin. A pace table stores information about the minimum inter-packet-gap for each connection that is coupled to the transmit DMA queue manager. A timer is coupled to the binning controller with a multi-bit continuous counter that increments at a predetermined time unit and wraps around after a predetermined amount of time.

Abstract translation: 描述了用于通过速率起搏多个队列来为不同连接量身定制的不同传输速率的步调引擎的系统和方法。 粗略地描述，速度引擎包括用于从发送DMA队列管理器接收队列的分档控制器，并且确定在工作仓，快速仓或慢速仓中存储和起搏的特定队列的最早允许时间。 步速表存储关于耦合到发送DMA队列管理器的每个连接的最小间隔间隔的信息。 定时器与具有多位连续计数器的分箱控制器耦合，该计数器以预定时间单位递增并在预定时间量之后卷绕。

公开(公告)号：US20060288129A1

公开(公告)日：2006-12-21

申请号：US11156228

申请日：2005-06-17

Applicant: Steve Pope ,  Derek Roberts ,  David Riddoch ,  Ching Yu ,  John Chiang ,  Der-Ren Chu

Inventor： Steve Pope ,  Derek Roberts ,  David Riddoch ,  Ching Yu ,  John Chiang ,  Der-Ren Chu

IPC: G06F13/28

CPC classification number: H04L49/901 ,  G06F13/28 ,  G06F13/385 ,  H04L49/90

Abstract: Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

公开(公告)号：US20060248234A1

公开(公告)日：2006-11-02

申请号：US11116018

申请日：2005-04-27

Applicant: Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

Inventor： Steve Pope ,  David Riddoch ,  Ching Yu ,  Derek Roberts

IPC: G06F15/16

CPC classification number: H04L63/10 ,  H04L47/50 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9063

Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

公开(公告)号：US07031305B1

公开(公告)日：2006-04-18

申请号：US09317156

申请日：1999-05-24

Applicant: Ching Yu ,  Xiaohua Zhuang ,  Bahadir Erimli ,  John M. Chiang ,  Shashank Merchant ,  Robert Williams ,  Edward Yang ,  Chandan Egbert ,  Vallath Nandakumar ,  Ian Lam ,  Eric Tsin-Ho Leung

Inventor： Ching Yu ,  Xiaohua Zhuang ,  Bahadir Erimli ,  John M. Chiang ,  Shashank Merchant ,  Robert Williams ,  Edward Yang ,  Chandan Egbert ,  Vallath Nandakumar ,  Ian Lam ,  Eric Tsin-Ho Leung

IPC: H04L12/28

CPC classification number: H04L49/351 ,  H04L49/205 ,  H04L49/3027 ,  H04L49/354

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

Abstract translation: 根据以太网（IEEE 802.3）协议，具有根据可编程信息灵活地分配存储器访问时隙以访问外部存储器的数据分组与各网络节点全双工通信的交换机端口的网络交换机。 外部存储器接口中的调度器根据从外部可编程数据存储设备写入指配表存储器的编程序列，将存储器访问时隙分配给相应的网络交换机端口。

公开(公告)号：US06651172B1

公开(公告)日：2003-11-18

申请号：US09321842

申请日：1999-05-28

Applicant: Ching Yu ,  Jeffrey Dwork ,  John Chiang ,  Hung-Duy Vo

Inventor： Ching Yu ,  Jeffrey Dwork ,  John Chiang ,  Hung-Duy Vo

IPC: G06F900

CPC classification number: G06F9/4411

Abstract: A novel method is provided for initializing a data processing system having registers programmable with configuration data read from a non-volatile memory at power-up. The method includes segmenting the non-volatile memory into a first portion for storing first data, and a second portion for storing second data having lower priority than the first data. The first portion is smaller than the second portion. The first data are read from the first portion to program a first group of registers. Thereafter, the second data are read from the second portion to program a second group of registers. As a result, a host is enabled to access the first group of registers, while the second data are being read from the second memory portion.

Abstract translation: 提供一种新颖的方法来初始化具有可编程的寄存器的数据处理系统，该寄存器在上电时从非易失性存储器读取的配置数据可编程。 该方法包括将非易失性存储器分割成用于存储第一数据的第一部分，以及用于存储具有比第一数据优先级低的第二数据的第二部分。 第一部分小于第二部分。 从第一部分读取第一数据以对第一组寄存器进行编程。 此后，从第二部分读取第二数据以编程第二组寄存器。 结果，主机能够访问第一组寄存器，而第二数据正在从第二存储器部分读取。

公开(公告)号：US06542512B1

公开(公告)日：2003-04-01

申请号：US09346745

申请日：1999-07-02

Applicant: Jenny Liu Fischer ,  Ching Yu ,  Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu ,  Ian Lam

Inventor： Jenny Liu Fischer ,  Ching Yu ,  Jerry Chun-Jen Kuo ,  Po-Shen Lai ,  Autumn Jane Niu ,  Ian Lam

IPC: H04L1228

CPC classification number: H04L49/901 ,  H04L47/50 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

Abstract translation: 分组交换网络中的网络交换机包括多个网络交换机端口，每个网络交换机端口被配置为在介质接口和网络交换机之间发送和接收数据分组。 网络交换机端口包括符合IEEE 802.3标准的传输状态机和接收状态机，其配置用于分别向介质接口（例如简化介质独立接口）发送和接收网络数据。 网络交换机端口还包括配置用于分别在发送和接收状态机与随机接入发送缓冲器和随机接入接收缓冲器之间选择性地传送网络数据的存储器管理单元。 发送状态机响应于发送发送数据中检测到的错误，向发送存储器管理单元输出清空发送缓冲器信号。 发送存储器管理单元响应于刷新发送缓冲器信号，将增加的发送缓冲器指针值设置为对应于存储在发送缓冲器中的下一个发送数据的缓冲器指针值。

公开(公告)号：US06504846B1

公开(公告)日：2003-01-07

申请号：US09315724

申请日：1999-05-21

Applicant: Ching Yu ,  Xiaohua Zhuang ,  Bahadir Erimli

Inventor： Ching Yu ,  Xiaohua Zhuang ,  Bahadir Erimli

IPC: H04L1256

CPC classification number: H04L47/15 ,  H04L49/30 ,  H04L49/3027 ,  H04L49/351 ,  H04L49/90

Abstract: A method and apparatus are disclosed for reclaiming frame buffers used to store data frames received by a network switch. The apparatus includes a multicopy queue for queuing entries corresponding to received data frames which must be transmitted by multiple output ports of the network switch, a free buffer queue for queuing frame pointers that identify locations in an external memory where reclaimed frame buffers are located, and a multicopy circuit that retrieves entries from the multicopy queue and determines if all copies of a received data frame have been transmitted by the specified output ports. The multicopy circuit also reclaims one or more frame buffers, based on the size of the received data frame. The present invention allows efficient reclaiming of frame buffers regardless of whether the received data frame is stored in a single frame buffer or multiple frame buffers.

Abstract translation: 公开了用于回收用于存储由网络交换机接收的数据帧的帧缓冲器的方法和装置。 该装置包括用于排队对应于必须由网络交换机的多个输出端口发送的数据帧的条目的多拷贝队列，用于排队识别在回收的帧缓冲器所在的外部存储器中的位置的空闲缓冲器队列，以及 多拷贝电路，从多拷贝队列检索条目，并确定接收的数据帧的所有副本是否已由指定的输出端口发送。 多拷贝电路还基于接收的数据帧的大小回收一个或多个帧缓冲器。 本发明允许帧缓冲器的有效回收，而不管接收的数据帧是存储在单个帧缓冲器还是多个帧缓冲器中。

公开(公告)号：US06477170B1

公开(公告)日：2002-11-05

申请号：US09315974

申请日：1999-05-21

Applicant: Jing Lu ,  Ching Yu

Inventor： Jing Lu ,  Ching Yu

IPC: H04L1240

CPC classification number: H04L49/40

Abstract: A method and apparatus for interfacing a central processing unit to a network switch with an external memory that transfers data to the network switch at a different clock speed than transfers of data to the central processing unit provides an interlocking mechanism to prevent overwriting of data and underflows from occurring. The interlocking of the state machines, accomplished by the idling and advancing of a processor state machine and an external memory state machine, prevents either one of the separate state machines from outrunning the other state machine.

Abstract translation: 用于将中央处理单元与网络交换机接口的方法和装置与外部存储器进行通信，该外部存储器以与将数据传送到中央处理单元不同的时钟速度将数据传送到网络交换机提供互锁机制，以防止覆盖数据和下溢 从发生。 通过处理器状态机和外部存储器状态机的空转和前进完成的状态机的联锁防止了单独的状态机中的任一个超出其他状态机。

公开(公告)号：US06463542B1

公开(公告)日：2002-10-08

申请号：US09321834

申请日：1999-05-28

Applicant: Ching Yu ,  Jerry Chun-Jen Kuo ,  Jeffrey Dwork ,  Din-I Tsai

Inventor： Ching Yu ,  Jerry Chun-Jen Kuo ,  Jeffrey Dwork ,  Din-I Tsai

IPC: G06F100

CPC classification number: G06F1/3209

Abstract: A novel method of power management is provided in a computer system having a network interface module including a buffer memory and a MAC block. The method includes determining whether the system is inactive during a predetermined time period. If so, activity of the MAC block is checked. If the MAC block is idle, the status of the buffer memory is determined. The system is placed into a power-down mode if the buffer memory is empty.

Abstract translation: 在具有包括缓冲存储器和MAC块的网络接口模块的计算机系统中提供了一种新颖的电源管理方法。 该方法包括在预定时间段内确定系统是否不活动。 如果是，则检查MAC块的活动。 如果MAC块空闲，则确定缓冲存储器的状态。 如果缓冲存储器为空，则将系统置于掉电模式。