公开(公告)号：US06639914B1

公开(公告)日：2003-10-28

申请号：US09419907

申请日：1999-10-18

Applicant: Ki-young Choi ,  Jung-ho Song

Inventor： Ki-young Choi ,  Jung-ho Song

IPC: H04L1240

CPC classification number: H04L12/40071 ,  G06F3/05 ,  H04L12/40117 ,  H04L29/06 ,  H04L69/22 ,  H04L69/32 ,  H04N5/4401 ,  H04N21/4108 ,  H04N21/43615 ,  H04N21/43632 ,  H04N21/44231

Abstract: An analog translator for the IEEE 1394 serial bus by which it is possible to use an analog device as a part of a home network when the analog device is connected to the IEEE 1394 serial bus and a translating method thereof are provided. The analog translator includes a plurality of ports to which analog devices are connected, a status register for showing which analog devices are connected, a configuration ROM for storing the information on the connected analog devices, a controller for setting the corresponding bit of a status register assigned to an analog device, reading the bit status of the set status register, and recording connection information of the analog device to the configuration ROM which refer to the bit status of the status register, when an analog device is connected to the port, a 1394 interfacing unit for receiving a packet data from the IEEE 1394 bus, checking whether the packet data corresponds to the node thereof, and disintegrating packet data and thus removing a header from the packet data when the packet data corresponds to the node thereof, a storing unit for storing payload data removed of a header from the 1394 interface, a destination unit extractor for decoding the payload data of the storing unit and extracting information on the destination analog device of the payload data, and a data translating unit for translating the payload data removed of the information on the destination analog device into analog signal. According to the present invention, it is possible to interface both analog and digital devices in realizing an IEEE 1394 home network.

Abstract translation: 一种用于IEEE 1394串行总线的模拟转换器，当模拟装置连接到IEEE 1394串行总线时，可以使用模拟装置作为家庭网络的一部分，并提供其翻译方法。 模拟转换器包括连接有模拟装置的多个端口，用于显示连接哪些模拟装置的状态寄存器，用于存储连接的模拟装置的信息的配置ROM，用于设置状态寄存器的相应位的控制器 分配给模拟设备，读取设置状态寄存器的位状态，并且当模拟设备连接到端口时，将模拟设备的连接信息记录到参考状态寄存器的位状态的配置ROM， 1394接口单元，用于从IEEE 1394总线接收分组数据，检查分组数据是否对应于其节点，并且当分组数据对应于其节点时，分解分组数据并从而从分组数据中去除报头，存储 用于存储从1394接口移除的报头的有效载荷数据的单元，用于解码st.d的有效载荷数据的目的地单元提取器 并且提取有效载荷数据的目的地模拟装置上的信息;以及数据转换单元，用于将去除的目标模拟装置上的信息的有效载荷数据转换为模拟信号。 根据本发明，可以在实现IEEE 1394家庭网络的同时将模拟和数字设备连接起来。

公开(公告)号：US06606320B1

公开(公告)日：2003-08-12

申请号：US09125318

申请日：1999-06-25

Applicant: Takashi Nomura ,  Hiroshi Takizuka

Inventor： Takashi Nomura ,  Hiroshi Takizuka

IPC: H04L1240

CPC classification number: H04L12/40058 ,  H04L2012/5618 ,  H04L2012/5679 ,  H04Q11/0478

Abstract: In a data transmission system, a data transmission method, a data transmitting apparatus and a data transmitting method according to this invention, in carrying out transmission of data at a predetermined transmit period from the server unit to the terminal equipment, an interrupt signal is generated at a scheduling period longer than a predetermined transmit period to carry out transmitting control of data every predetermined transmit period on the basis of quantity of transmittable data within one scheduling period unit. Thus, overhead of isochronous packet is reduced, thus making it possible to improve transmission efficiency.

Abstract translation: 在根据本发明的数据传输系统，数据传输方法，数据发送装置和数据发送方法中，在从服务器单元到终端设备的预定发送周期执行数据传输时，产生中断信号 在比预定的发送周期长的调度时段，基于一个调度周期单元内的可发送数据的量，每隔预定的发送周期进行数据的发送控制。 因此，同步分组的开销降低，从而可以提高传输效率。

公开(公告)号：US06463072B1

公开(公告)日：2002-10-08

申请号：US09473570

申请日：1999-12-28

Applicant: Gilbert Wolrich ,  Debra Bernstein ,  Matthew Adiletta

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Matthew Adiletta

IPC: H04L1240

CPC classification number: H04L49/901 ,  H04L49/90

Abstract: A router includes a communications bus, a second bus, and at least two processors. The second bus transfers ready status data from ports connected to the communications bus. The processors are connected to the communications and second busses. One of the processors controls the communications bus at each time. Each processor transfers control of the communications bus to another processor in response to receiving a request for control from the other processor.

Abstract translation: 路由器包括通信总线，第二总线和至少两个处理器。 第二个总线从连接到通信总线的端口传送就绪状态数据。 处理器连接到通信和第二总线。 其中一个处理器每次都控制通讯总线。 响应于从另一处理器接收到控制请求，每个处理器将通信总线的控制传送到另一个处理器。

公开(公告)号：US06272146B1

公开(公告)日：2001-08-07

申请号：US08965365

申请日：1997-11-06

Applicant: Ronald John Bowater ,  Michael Cobbett ,  Robert Michael Jordan ,  Andrew James Ritchie

Inventor： Ronald John Bowater ,  Michael Cobbett ,  Robert Michael Jordan ,  Andrew James Ritchie

IPC: H04L1240

CPC classification number: H04Q11/04 ,  H04Q2213/13003 ,  H04Q2213/1305 ,  H04Q2213/1307 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13109 ,  H04Q2213/13176 ,  H04Q2213/13179 ,  H04Q2213/13203 ,  H04Q2213/13204 ,  H04Q2213/13272 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/13378 ,  H04Q2213/13392 ,  H04Q2213/13396

Abstract: A bus connection controller in a voice processing is for managing the connection of a timeslot on a time-division multiplex (TDM) bus to a port on an adapter. The voice processing system includes basic time-division multiplex (TDM) connection management to enable the coordination of connections between resources such as channels on line cards (SPacks or VPacks), and channels on digital signal processor (DSPs) cards that provide, amongst others things, voice recognition, text-to-speech, fax capabilities and so on. Problems are encountered when a telephone call in a voice processing system ends suddenly because one of the callers hangs up. If the telephony channel has connections with other channels or resources via a TDM bus, callers may hear spurious data. To address this problem each call is associated with its corresponding connection on the TDM bus and each connection is associated with its connection details including the adapters and ports involved in connecting the calls. When one of the calls ends all the relevant ports involved with the connection are immediately disconnected.

Abstract translation: 语音处理中的总线连接控制器用于管理时分复用（TDM）总线上的时隙与适配器上的端口的连接。 语音处理系统包括基本的时分多路复用（TDM）连接管理，以实现诸如线路卡（SPack或VPack）之间的信道之类的资源之间的连接的协调，以及数字信号处理器（DSP） 事物，语音识别，文字转语音，传真功能等。 当语音处理系统中的电话呼叫由于其中一个呼叫者挂断而突然结束时遇到问题。 如果电话信道通过TDM总线与其他信道或资源连接，则呼叫者可能会收到虚假数据。 为了解决这个问题，每个呼叫都与其在TDM总线上的对应连接相关联，并且每个连接与其连接细节相关联，包括连接呼叫所涉及的适配器和端口。 当其中一个呼叫结束时，连接涉及的所有相关端口立即断开连接。

公开(公告)号：US06246692B1

公开(公告)日：2001-06-12

申请号：US09092350

申请日：1998-06-05

Applicant: William Dai ,  Jason Chao ,  Cheng-chung Shih

Inventor： William Dai ,  Jason Chao ,  Cheng-chung Shih

IPC: H04L1240

CPC classification number: H04L49/102 ,  H04L12/42 ,  H04L49/201 ,  H04L49/3018 ,  H04L49/351

Abstract: A packet switching fabric includes a data ring, a control ring, a plurality of network links each coupled to at least one network node, and a plurality of switching devices coupled together by the data ring and the control ring so that the network links can be selectively communicatively coupled. Each of the switching devices includes: a data ring sub-system for transmitting and receiving bursts of data via data ring channels concurrently active on the data ring; a network interface coupled to the data ring sub-system and having at least one network port for transmitting and receiving data packets to and from one of the network links, the network interface also having a packet buffer for storing the data packets, the packet buffer providing bursts of packet data to the data ring sub-system via a plurality of concurrently active packet buffer channels; and a control ring sub-system coupled to the data ring sub-system and to the network interface and being responsive to control messages received from an adjacent one of the devices via the control ring, and operative to develop and transmit the control messages to an adjacent one of the devices via the control ring, the control messages for reserving bandwidth resources used in setting up and controlling the data ring channels and the packet buffer channels, the control ring sub-system also being operative to perform queuing operations for controlling the transfer of the bursts of packet data from the packet buffer to the data ring sub-system.

Abstract translation: 分组交换结构包括数据环，控制环，每个耦合到至少一个网络节点的多个网络链路，以及由数据环和控制环耦合在一起的多个交换设备，使得网络链路可以是 选择性地通信耦合。 每个交换设备包括：数据环子系统，用于经由数据环上同时有效的数据环通道发送和接收数据; 耦合到所述数据环子系统并且具有用于向所述网络链路之一发送和接收数据分组的至少一个网络端口的网络接口，所述网络接口还具有用于存储所述数据分组的分组缓冲器，所述分组缓冲器 通过多个同时活动的分组缓冲信道向数据环子系统提供分组数据的突发; 以及控制环子系统，其耦合到所述数据环子系统和所述网络接口，并且响应于经由所述控制环从所述设备中的相邻设备接收的控制消息，并且可操作地开发并将所述控制消息发送到 通过控制环相邻的一个设备，用于保留用于设置和控制数据环通道和分组缓冲器通道的带宽资源的控制消息，控制环子系统还可操作以执行用于控制传输的排队操作 从分组缓冲器到数据环子系统的分组数据的突发。

公开(公告)号：US06816504B1

公开(公告)日：2004-11-09

申请号：US09191157

申请日：1998-11-13

Applicant: Marc David Erickson

Inventor： Marc David Erickson

IPC: H04L1240

CPC classification number: H04L12/42

Abstract: Briefly, in accordance with one embodiment of the invention, a method of using a bypass buffer in a node coupled to a ringlet includes the steps of: writing a packet of binary digital signals on the ringlet into the bypass buffer; and retaining the packet of binary digital signals in the bypass buffer for a predetermined amount of time before transferring the packet to the ringlet. Briefly, in accordance with another embodiment, a node to be coupled to a ringlet includes: a transmit buffer and a receive buffer. The transmit and receive buffers are coupled in a configuration to transfer binary digital signals between the node and the ringlet via the transmit and receive buffers. The configuration further includes a bypass buffer to temporarily queue binary digital signals passing through the node. The bypass buffer is further coupled in the configuration to retain a packet of binary digital signals for a predetermined amount of time before transferring the packet to the ringlet. Briefly, in accordance with yet one more embodiment, a node to be coupled to a ringlet includes a bypass buffer. The bypass buffer is able to be coupled to the ringlet to temporarily queue data signals from the ringlet. Digital logic circuitry coupled to the bypass buffer includes a head pointer for the bypass buffer. The bypass buffer is coupled to the head pointer to retain a packet of data signals for a predetermined amount of time before transferring the packet to the ringlet.

Abstract translation: 简而言之，根据本发明的一个实施例，在耦合到小环的节点中使用旁路缓冲器的方法包括以下步骤：将二进制数字信号分组写入到旁路缓冲器中; 并且在将分组传送到小环之前将二进制数字信号包保留在旁路缓冲器中预定的时间量。简而言之，根据另一个实施例，要耦合到小环的节点包括：发送缓冲器和接收器 缓冲。 发送和接收缓冲器被配置成经由发送和接收缓冲器在节点和小环之间传送二进制数字信号。 该配置还包括旁路缓冲器，用于临时排队通过节点的二进制数字信号。 旁路缓冲器在该配置中进一步耦合以在将分组传送到小环之前保持二进制数字信号分组达预定时间量。简而言之，根据又一个实施例，要耦合到小环的节点包括 旁路缓冲区。 旁路缓冲器能够耦合到小环以临时排队来自小环的数据信号。 耦合到旁路缓冲器的数字逻辑电路包括用于旁路缓冲器的头指针。 旁路缓冲器耦合到头指针，以在将分组传送到小环之前保持数据信号分组达预定的时间量。

公开(公告)号：US06804250B2

公开(公告)日：2004-10-12

申请号：US09251299

申请日：1999-02-17

Applicant: Shinichi Hatae ,  Takashi Kobayashi ,  Mitsuo Niida ,  Shinji Ohnishi

Inventor： Shinichi Hatae ,  Takashi Kobayashi ,  Mitsuo Niida ,  Shinji Ohnishi

IPC: H04L1240

CPC classification number: H04L12/40052 ,  H04L12/40117 ,  H04L12/40123 ,  H04L12/6418 ,  H04L29/06027 ,  H04L29/12009 ,  H04L29/12207 ,  H04L29/12783 ,  H04L29/12801 ,  H04L47/10 ,  H04L47/13 ,  H04L47/32 ,  H04L49/90 ,  H04L49/9052 ,  H04L61/20 ,  H04L61/35 ,  H04L61/6004 ,  H04L65/1069 ,  H04L65/4076 ,  H04L65/602 ,  H04L69/32 ,  H04L69/329 ,  H04L2012/6486

Abstract: Provided is a communication system for logically connecting a source node and one or more destination nodes, and for controlling data communication between the individual nodes by employing a connection ID that is used to identity the logical connection relationship. The communication system may comprise a source node adapted to transmit data packets, a destination node adapted to receive the data packets transmitted from the source node, and a controller adapted to manage a logical connection between the source node and the destination node, the destination node being adapted to abort communication between the source node and the destination node if the destination node received an abort packet transmitted from the controller, and the destination node being adapted to disconnect the logical connection after the communication is aborted by the abort packet. The source node itself, and methods of using the system and that node, are also individual aspects of what is disclosed.

Abstract translation: 提供了用于逻辑地连接源节点和一个或多个目的地节点的通信系统，并且用于通过采用用于标识逻辑连接关系的连接ID来控制各个节点之间的数据通信。 通信系统可以包括适于发送数据分组的源节点，适于接收从源节点发送的数据分组的目的地节点和适于管理源节点和目的节点之间的逻辑连接的控制器，目的地节点 如果所述目的地节点接收到从所述控制器发送的中止分组，则适于中止所述源节点和所述目的地节点之间的通信，并且所述目的地节点适于在所述通信被所述中止分组中止之后断开所述逻辑连接。 源节点本身以及使用系统和该节点的方法也是所公开的单独方面。

公开(公告)号：US06785284B1

公开(公告)日：2004-08-31

申请号：US09637334

申请日：2000-08-10

Applicant: Gunnar Hagen

Inventor： Gunnar Hagen

IPC: H04L1240

CPC classification number: G06F13/30 ,  G06F13/287 ,  H04L2012/5667

Abstract: A DMA system includes a plurality of transmit-receive pairs (102, 104) for communicating on a bus. A DMA controller (108) supervises bus handling. The DMA controller (108) includes a priority controller (114), a bus sniffer (112), and a context machine (116). The bus sniffer (112) and context machine (116) identify block transfers as frame or cell transfers and supervise interleaving. The priority controller (114) resolves the priority of each of the constituent transfers of the frame or cell block transfers using a matrix of priority tokens.

Abstract translation: DMA系统包括用于在总线上通信的多个发送 - 接收对（102,104）。 DMA控制器（108）监督总线处理。 DMA控制器（108）包括优先级控制器（114），总线嗅探器（112）和上下文机器（116）。 总线嗅探器（112）和上下文机器（116）将块传输识别为帧或小区传输并监督交织。 优先级控制器（114）使用优先级令牌矩阵来解决帧或单元块传输的每个组成传输的优先级。

公开(公告)号：US06693901B1

公开(公告)日：2004-02-17

申请号：US09544099

申请日：2000-04-06

Applicant: Charles Calvin Byers ,  Stephen Joseph Hinterlong ,  Robert Allen Novotny

Inventor： Charles Calvin Byers ,  Stephen Joseph Hinterlong ,  Robert Allen Novotny

IPC: H04L1240

CPC classification number: H04L49/405 ,  H04Q11/0478 ,  H05K1/14

Abstract: An electronic system for networking, switching or computing includes a backplane-based interconnection system (100). The system includes a backplane (102) with a plurality of traces coupled to slots for receiving circuit packs (104a-d). The backplane traces are configured to form point-to-point connections (106a-f) from one slot of the backplane to every other slot of the backplane. A hub circuit (110) is provided on each circuit pack for coupling the circuit pack to the point-to-point connections in the backplane. Circuit packs communicate via direct connections over the point-to-point connections or indirectly by sending traffic through point-to-point connections and hub circuits.

Abstract translation: 一种用于网络，交换或计算的电子系统包括基于背板的互连系统（100）。 该系统包括具有耦合到用于接收电路板（104a-d）的插槽的多个迹线的背板（102）。 底板轨迹被配置为形成从背板的一个槽到背板的每隔一个槽的点对点连接（106a-f）。 在每个电路板上设置集线器电路（110），用于将电路板耦合到背板中的点对点连接。 电路板通过点对点连接的直接连接进行通信，或间接通过点对点连接和集线器电路发送流量进行通信。

公开(公告)号：US06466549B1

公开(公告)日：2002-10-15

申请号：US09290356

申请日：1999-04-12

Applicant: Myron P. Hattig

Inventor： Myron P. Hattig

IPC: H04L1240

CPC classification number: H04L12/2803 ,  H04L12/2809 ,  H04L12/40091 ,  H04L12/46 ,  H04L41/00 ,  H04L67/16 ,  H04L69/40 ,  H04L2012/285

Abstract: A method and apparatus for providing broadcast discovery in a network having one or more 1394 buses is disclosed. Devices connected to a bus generate advertised discovery information upon either a reset of the bus or a receipt of a solicit packet sent to all devices in the network by a discovering device. The devices generate the advertised discovery information upon the receipt of the solicit packet if the solicit packet contains either a global bus identifier or a bus identifier associated with the bus to which the devices are connected. The discovering device receives the advertised discovery information sent by the devices. Based on the advertised discovery information, the discovering device maintains a list of devices and services included within the devices.

Abstract translation: 公开了一种在具有一个或多个1394总线的网络中提供广播发现的方法和装置。 连接到总线的设备在总线的复位或通过发现设备发送到网络中的所有设备的请求包的接收时产生通告的发现信息。 如果请求分组包含全局总线标识符或与设备连接到的总线相关联的总线标识符，则在接收到请求分组时，设备生成通告的发现信息。 发现设备接收设备发送的发布的发现信息。 基于发布的发现信息，发现设备维护包括在设备内的设备和服务的列表。