Abstract:
A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.
Abstract:
A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.
Abstract:
An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.