公开(公告)号：US07216183B2

公开(公告)日：2007-05-08

申请号：US10885436

申请日：2004-07-06

Applicant: Kuan-Jui Ho ,  Jui-Ming Wei

Inventor： Kuan-Jui Ho ,  Jui-Ming Wei

IPC: G06F13/14 ,  G06F13/20

CPC classification number: G06F13/4027

Abstract: A method for facilitating read completion in a computer system supporting write posting operations. A posted memory write and its associated tag both need to be buffered, where the associated tag is designated to a master of a local bus originating the posted memory write. When a read request moving in an opposite direction of the posted memory write is detected, the read request is checked to identify which master of the local bus is addressed. A destination tag is then assigned to the read request contingent upon the currently addressed master. Further, the destination tag of the read request is compared with the associated tag of the posted memory write. If the destination tag of the read request differs from the associated tag of the posted memory write, the read request can be completed directly regardless of the outstanding posted writes.

Abstract translation: 一种便于在支持写入过帐操作的计算机系统中的读取完成的方法。 发布的存储器写及其关联的标签都需要被缓冲，其中相关联的标签被指定给源自发布的存储器写入的本地总线的主机。 当检测到以相反方向移动的读取请求时，检查读取请求以识别本地总线的哪个主机被寻址。 然后将目的地标签分配给读取请求，取决于当前寻址的主机。 此外，将读取请求的目的地标签与已发布的存储器写入的关联标签进行比较。 如果读取请求的目的地标签与已发布的存储器写入的关联标签不同，则可以直接完成读取请求，而不管未发布的写入如何。

公开(公告)号：US20060294316A1

公开(公告)日：2006-12-28

申请号：US11328105

申请日：2006-01-10

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F12/00

CPC classification number: G06F12/0862 ,  G06F2212/306

Abstract: A selectively prefetch method is applied on a bridge module. The bridge module has a prefetch controller and a memory controller, and the prefetch controller at least includes a source comparison register for storing at least one determining reference data. The selectively prefetch method includes the following steps of: receiving an instruction by the bridge module, determining whether the source of the instruction matches a specific source or not by the prefetch controller according to the determining reference data, executing a prefetch action by the prefetch controller through the memory controller when the source of the instruction matches the specific source, and not executing the prefetch action by the prefetch controller when the source of the instruction does not match the specific source.

Abstract translation: 在桥模块上应用选择性预取方法。 桥模块具有预取控制器和存储器控制器，并且预取控制器至少包括用于存储至少一个确定参考数据的源比较寄存器。 选择性预取方法包括以下步骤：接收桥模块的指令，根据确定参考数据，由预取控制器确定指令源是否与特定源匹配，执行预取控制器的预取操作 当指令源与特定源匹配时，通过存储器控制器，当指令源与特定源不匹配时，预取指令不执行预取操作。

公开(公告)号：US20060224855A1

公开(公告)日：2006-10-05

申请号：US11174462

申请日：2005-07-06

Applicant: Kuan-Jui Ho ,  Hsiu Chu

Inventor： Kuan-Jui Ho ,  Hsiu Chu

IPC: G06F12/00

CPC classification number: G06F13/4027

Abstract: A device for accessing a memory includes a memory module, a CPU and a north bridge chipset. The memory module has an ordinary area and a redundant area. The CPU outputs redundant address data. The north bridge chipset includes a memory module controller, a data register and a pointer. The pointer records the redundant address data. When a writing procedure is performed, the data register records to-be-stored data, and the memory module controller stores the to-be-stored data to a first physical address of the redundant area according to the pointer and the data register. In addition, when a reading procedure is performed, the data register records a to-be-read amount, and the memory module controller reads to-be-read data from a second physical address of the redundant area according to the pointer and the data register.

Abstract translation: 用于访问存储器的设备包括存储器模块，CPU和北桥芯片组。 存储器模块具有普通区域和冗余区域。 CPU输出冗余地址数据。 北桥芯片组包括存储器模块控制器，数据寄存器和指针。 指针记录冗余地址数据。 当执行写入过程时，数据寄存器记录要存储的数据，并且存储器模块控制器根据指针和数据寄存器将待存储数据存储到冗余区的第一物理地址。 此外，当执行读取过程时，数据寄存器记录待读取量，并且存储器模块控制器根据指针和数据从冗余区域的第二物理地址读取要读取的数据 寄存器。

公开(公告)号：US20060212638A1

公开(公告)日：2006-09-21

申请号：US11263970

申请日：2005-11-02

Applicant: Hsiu Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

Inventor： Hsiu Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

IPC: G06F13/36

CPC classification number: G06F9/4411

Abstract: A motherboard includes a south-bridge chipset, a north-bridge chipset and a central processor unit (CPU). The south-bridge chipset generates at least control-setting data. The north-bridge chipset has a reset register for controlling the north-bridge chipset to generate a reset signal and a control-set resister for storing the control-setting data generated by the south-bridge chipset. The CPU has a plurality of configuration parameters. The configuration parameters of the CPU are reset in accordance with the reset signal, and the control-setting data is written into the CPU by the north-bridge chipset to set one of the configuration parameters of the CPU.

Abstract translation: 主板包括南桥芯片组，北桥芯片组和中央处理器单元（CPU）。 南桥芯片组至少产生控制设置数据。 北桥芯片组具有用于控制北桥芯片组以产生复位信号的复位寄存器和用于存储由南桥芯片组产生的控制设置数据的控制集合寄存器。 CPU具有多个配置参数。 CPU的配置参数根据复位信号复位，控制设置数据由北桥芯片组写入CPU，以设置CPU的一个配置参数。

公开(公告)号：US20060212615A1

公开(公告)日：2006-09-21

申请号：US11127113

申请日：2005-05-12

Applicant: Kuan-Jui Ho ,  Hsiu Chu

Inventor： Kuan-Jui Ho ,  Hsiu Chu

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F13/28 ,  G06F12/0879

Abstract: A device for burst reading/writing memory data includes a memory module and a north bridge chipset. The device is used for executing a power on self test (POST). The memory module has a plurality of memory cells and the north bridge chipset includes a programmable register module and a memory module controller, wherein the programmable register module stores at least one set of default information. The memory module controller performing burst read/write on the memory cells according to the default information stored in the programmable register module.

Abstract translation: 用于突发读/写存储器数据的装置包括存储器模块和北桥芯片组。 该设备用于执行电源自检（POST）。 存储器模块具有多个存储器单元，并且北桥芯片组包括可编程寄存器模块和存储器模块控制器，其中可编程寄存器模块存储至少一组默认信息。 存储器模块控制器根据存储在可编程寄存器模块中的默认信息在存储器单元上执行脉冲串读/写。

公开(公告)号：US07757130B2

公开(公告)日：2010-07-13

申请号：US11836249

申请日：2007-08-09

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F11/00

CPC classification number: G06F11/1076

Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal.

Abstract translation: 计算机系统中的多个硬盘驱动器的RAID控制包括对写入的数据执行容错数据计算操作。 通过访问存储在一个硬盘驱动器中的数据，检测已经从硬盘驱动器发送到计算机系统的数据流的部分数据长度来确定用于执行容错数据计算操作的定时，发出 当数据长度已经达到小于数据流的总长度的单位长度时，触发信号，然后响应于触发信号，以数据的单位长度执行容错数据计算操作。

公开(公告)号：US07469335B2

公开(公告)日：2008-12-23

申请号：US11135203

申请日：2005-05-23

Applicant: Hsiu-Ming Chu ,  Kuan-Jui Ho

Inventor： Hsiu-Ming Chu ,  Kuan-Jui Ho

IPC: G06F9/24

CPC classification number: G06F9/4403

Abstract: A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin A31 of the processor, and a reset signal is delivered to the processor while the pin A31 is at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.

Abstract translation: 一种用于计算机系统的开机方法，包括支持超线程的处理器，只读存储器（ROM）和主存储器，其中所述处理器包括高速缓冲存储器，并且所述ROM包括BIOS代码。 上电方法包括以下步骤。 首先，处理器在超线程禁用模式下初始化。 然后将BIOS代码从ROM复制到高速缓冲存储器，并且通过在其中执行BIOS代码来初始化主存储器。 此后，在主存储器初始化之后，处理器在启用超线程的模式下被重新初始化。 处理器包括第一逻辑单元和第二逻辑单元。 当初始化处理器时，将第一电位施加到处理器的引脚A31，并且当引脚A31处于第一电位时，复位信号被传送到处理器，使得处理器在超线程禁止模式下被初始化。

公开(公告)号：US20080082854A1

公开(公告)日：2008-04-03

申请号：US11611323

申请日：2006-12-15

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F1/00

CPC classification number: G06F1/08

Abstract: A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Abstract translation: 公开了一种用于调整时钟频率的方法。 该方法包括在调谐时钟频率的同时停止中央处理单元（CPU），由此产生具有调谐时钟频率的多个时钟信号。

公开(公告)号：US07334118B2

公开(公告)日：2008-02-19

申请号：US11126131

申请日：2005-05-10

Applicant: Hsiu-Ming Chu ,  Kuan-Jui Ho

Inventor： Hsiu-Ming Chu ,  Kuan-Jui Ho

IPC: G06F15/177

CPC classification number: G06F13/4027 ,  G06F1/24 ,  Y02D10/14 ,  Y02D10/151

Abstract: A computer reset method activated by a South Bridge to directly reset a Central Processing Unit (CPU). First, a trigger signal is received. A CPU reset signal is delivered by the South Bridge when receiving the trigger signal. Thereafter, the CPU is reset when receiving the CPU reset signal from the South Bridge via a North Bridge.

Abstract translation: 由南桥激活的计算机复位方法直接复位中央处理单元（CPU）。 首先，接收触发信号。 接收到触发信号时，南桥交付CPU复位信号。 此后，当通过北桥接收来自南桥的CPU复位信号时，CPU被复位。

公开(公告)号：US20080040629A1

公开(公告)日：2008-02-14

申请号：US11836249

申请日：2007-08-09

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F11/14

CPC classification number: G06F11/1076

Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal

Abstract translation: 计算机系统中的多个硬盘驱动器的RAID控制包括对写入的数据执行容错数据计算操作。 通过访问存储在一个硬盘驱动器中的数据，检测已经从硬盘驱动器发送到计算机系统的数据流的部分数据长度来确定用于执行容错数据计算操作的定时，发出 当数据长度已经达到小于数据流的总长度的单位长度时，触发信号，然后响应于触发信号以单位长度的数据执行容错数据计算操作