公开(公告)号：US20130103872A1

公开(公告)日：2013-04-25

申请号：US13485174

申请日：2012-05-31

Applicant: Kuan-Jui Ho ,  Yi-Hsiang Wang ,  Wen-Pin Chiang

Inventor： Kuan-Jui Ho ,  Yi-Hsiang Wang ,  Wen-Pin Chiang

IPC: G06F13/24

CPC classification number: G06F9/4812 ,  G06F9/5033

Abstract: A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to each of the CPUs. The chipset is configured for receiving an interrupt request sent from an external hardware device and judging whether or not a task type corresponding to the interrupt request has ever been performed by any one of the CPUs. If a judging result thereof is yes, the chipset assigns the interrupt request to the CPU that has ever performed the task type, so as to perform a corresponding interrupt task.

Abstract translation: 提供了一种用于分发其中断任务的计算机装置和方法。 计算机装置具有多个CPU和芯片组，并且该芯片组电耦合到每个CPU。 芯片组被配置为用于接收从外部硬件设备发送的中断请求，并判断任何一个CPU是否曾执行与中断请求对应的任务类型。 如果其判断结果为是，则芯片组将中断请求分配给已经执行任务类型的CPU，以便执行相应的中断任务。

公开(公告)号：US07886310B2

公开(公告)日：2011-02-08

申请号：US11832253

申请日：2007-08-01

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F13/00

CPC classification number: G06F11/1076 ,  G06F2211/1054

Abstract: In a computer system including a central processing unit, a system memory, a south bridge module, a north bridge module and multiple hard disk drives, a RAID control function is exhibited. The method includes steps of: issuing a command addressing to the south bridge module by the central processing unit; and performing a fault-tolerant computing operation in the north bridge module while exempting from transmitting the command to the south bridge module when the command contains a specified address data.

Abstract translation: 在包括中央处理单元，系统存储器，南桥模块，北桥模块和多个硬盘驱动器的计算机系统中，显示了RAID控制功能。 该方法包括以下步骤：由中央处理单元向南桥模块发出寻址命令; 并且在所述命令包含指定的地址数据时，在所述北桥模块中执行容错计算操作，同时不向所述南桥模块发送所述命令。

公开(公告)号：US07661007B2

公开(公告)日：2010-02-09

申请号：US11611323

申请日：2006-12-15

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F1/26

CPC classification number: G06F1/08

Abstract: A method for adjusting clock frequency is disclosed. The method includes halting a central processing unit (CPU) while tuning a clock frequency, thereby enabling multiple clock signals with the tuned clock frequency to be generated.

Abstract translation: 公开了一种用于调整时钟频率的方法。 该方法包括在调谐时钟频率的同时停止中央处理单元（CPU），由此产生具有调谐时钟频率的多个时钟信号。

公开(公告)号：US20070283059A1

公开(公告)日：2007-12-06

申请号：US11604812

申请日：2006-11-28

Applicant: Kuan-Jui Ho ,  Min-Hung Chen ,  Hsiou-Ming Chu

Inventor： Kuan-Jui Ho ,  Min-Hung Chen ,  Hsiou-Ming Chu

IPC: G06F13/00

CPC classification number: G06F13/102

Abstract: The present invention relates to a method for configuring a Peripheral Component Interconnect Express (PCIE). A plurality of PCIE parameters are stored in a storage unit. When a computer system starts up, a North Bridge chip is driven to read the PCIE parameters in the storage unit for configuring the PCIE. According to the configuration method of the present invention, when the computer system starts up, the North Bridge chip and the storage unit are enabled first. Then, the North Bridge chip is driven to read the PCIE parameters. Finally, the North Bridge chip proceeds with initialization according to the PCIE parameters to configure PCIE.

Abstract translation: 本发明涉及一种用于配置外围组件互连Express（PCIE）的方法。 多个PCIE参数被存储在存储单元中。 当计算机系统启动时，驱动北桥芯片读取存储单元中的PCIE参数以配置PCIE。 根据本发明的配置方法，当计算机系统启动时，首先启用北桥芯片和存储单元。 然后，驱动北桥芯片读取PCIE参数。 最后，北桥芯片根据PCIE参数进行初始化，配置PCIE。

公开(公告)号：US20070156934A1

公开(公告)日：2007-07-05

申请号：US11619047

申请日：2007-01-02

Applicant: Kuan-Jui Ho ,  Wen-Yun Chen

Inventor： Kuan-Jui Ho ,  Wen-Yun Chen

IPC: G06F13/42

CPC classification number: G06F13/4027

Abstract: A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at least one reset signal generator. While a hot rest package cannot be executed by the high-speed PCI device, the host controller chipset can respectively transmit a trigger signal and a PCI reset signal to each corresponding reset signal generator through a trigger signal line and a PCI reset signal line, and further the reset signal generator operates to generate a basic resetting signal. Finally, the basic resetting signal will be transmitted to the corresponding high-speed PCI device through a basic reset signal line such that the system can be used to operate the basic resetting action without restarting power.

Abstract translation: 提供具有复位功能的高速PCI接口系统及其复位方法。 接口系统包括主机控制器芯片组，至少一个高速PCI设备和至少一个复位信号发生器。 虽然高速PCI设备不能执行热休息包，但是主机控制器芯片组可以通过触发信号线和PCI复位信号线分别将触发信号和PCI复位信号发送到每个相应的复位信号发生器，以及 此外，复位信号发生器操作以产生基本复位信号。 最后，基本的复位信号将通过基本的复位信号线传输到相应的高速PCI设备，使得系统可以用来操作基本的复位动作而不重新启动电源。

公开(公告)号：US07162568B2

公开(公告)日：2007-01-09

申请号：US10757464

申请日：2004-01-15

Applicant: Chung-Ching Huang ,  Kuan-Jui Ho

Inventor： Chung-Ching Huang ,  Kuan-Jui Ho

IPC: G06F12/00

CPC classification number: G06F11/2284

Abstract: An apparatus and method of flash ROM management. The apparatus comprises a storage device, a strapping component and a process unit. The storage device stores multiple address records comprising an identity and an address range associated with a flash ROM. The strapping component is configured to output a signal to determine flash ROM type. The process unit receives a memory access request with an access range from the CPU and the signal from the strapping component queries the identity by matching the access range and the address range, and finally executes an LPC 1.1 memory access instruction with the identity and the access range corresponding to the memory cycle.

Abstract translation: 一种闪存ROM管理的设备和方法。 该装置包括存储装置，捆扎部件和处理单元。 存储设备存储包括与快闪ROM相关联的身份和地址范围的多个地址记录。 绑带组件配置为输出信号以确定闪存ROM类型。 处理单元从CPU接收具有访问范围的存储器访问请求，并且来自绑带组件的信号通过匹配访问范围和地址范围来查询身份，并且最终执行具有身份和访问权的LPC 1.1存储器访问指令 范围对应于存储器周期。

公开(公告)号：US20060294404A1

公开(公告)日：2006-12-28

申请号：US11316708

申请日：2005-12-27

Applicant: Kuan-Jui Ho

Inventor： Kuan-Jui Ho

IPC: G06F1/26

CPC classification number: G06F1/3203

Abstract: A method of power management of a CPU connects to a plurality of host bridges. The method is applied to a CPU connecting to the host bridges. When the host bridges are detected as no bus master signal being received, a command is transmitted to force the host bridges not to transmit the bus master signal to the CPU when they receive the bus master signal. After the CPU enters the C3 state, if the host bridges are detected that any one of the host bridges receives the bus master signal, the CPU is forced to quit the C3 state, and the host bridges are forced to transmit the bus master signal to the CPU.

公开(公告)号：US20060129789A1

公开(公告)日：2006-06-15

申请号：US11135203

申请日：2005-05-23

Applicant: Hsiu-Ming Chu ,  Kuan-Jui Ho

Inventor： Hsiu-Ming Chu ,  Kuan-Jui Ho

IPC: G06F9/00

CPC classification number: G06F9/4403

Abstract: A power-on method for a computer system comprising a processor supporting Hyper-Threading, a Read Only Memory (ROM) and a main memory, wherein the processor comprises a cache memory and the ROM comprises BIOS codes. The power-on method comprises the following steps. First, the processor is initialized in a Hyper-Threading disabled mode. The BIOS codes is then copied from the ROM to the cache memory, and the main memory is initialized by executing the BIOS codes therein. Thereafter, the processor is re-initialized in a Hyper-Threading enabled mode after the main memory is initialized. The processor comprises a first logic unit and a second logic unit. When initializing the processor, a first potential is applied to pin A31 of the processor, and a reset signal is delivered to the processor while the pin A31 is at the first potential, such that the processor is initialized in the Hyper-Threading disabled mode.

Abstract translation: 一种用于计算机系统的开机方法，包括支持超线程的处理器，只读存储器（ROM）和主存储器，其中所述处理器包括高速缓冲存储器，并且所述ROM包括BIOS代码。 上电方法包括以下步骤。 首先，处理器在超线程禁用模式下初始化。 然后将BIOS代码从ROM复制到高速缓冲存储器，并且通过在其中执行BIOS代码来初始化主存储器。 此后，在主存储器初始化之后，处理器在启用超线程的模式下被重新初始化。 处理器包括第一逻辑单元和第二逻辑单元。 当初始化处理器时，第一个电位被施加到处理器的引脚A 31，并且当引脚A 31处于第一个电位时，复位信号被传送到处理器，使得处理器在超线程禁用中被初始化 模式。

公开(公告)号：US20060103609A1

公开(公告)日：2006-05-18

申请号：US11280343

申请日：2005-11-17

Applicant: Kuan-Jui Ho ,  Ching-Jan Chao ,  Chun-Te Lu

Inventor： Kuan-Jui Ho ,  Ching-Jan Chao ,  Chun-Te Lu

IPC: G09G3/30

CPC classification number: G09G3/3216 ,  G09G3/2022 ,  H01L51/52

Abstract: Methods for driving a display consisting of organic bistable light-emitting devices (OBLEDs), each corresponding to one pixel in the display. An exemplary method comprises respectively writing a signal during a sub-frame, into each selected OBLED, applying a certain voltage to all the OBLEDs such that the brightness of each OBLED is determined by the signal stored therein, nd erasing the signals stored in all the OBLEDs.

Abstract translation: 用于驱动由有机双稳态发光器件（OBLED）组成的显示器的方法，每个对应于显示器中的一个像素。 一种示例性方法包括分别在子帧期间将信号写入每个选定的OBLED中，向所有OBLED施加一定电压，使得每个OBLED的亮度由存储在其中的信号确定，并且擦除存储在所有OBLED中的信号 OBLEDs。

公开(公告)号：US20060053273A1

公开(公告)日：2006-03-09

申请号：US11001148

申请日：2004-11-30

Applicant: Hsiu-Ming Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

Inventor： Hsiu-Ming Chu ,  Kuan-Jui Ho ,  Chung-Che Wu

IPC: G06F9/00

CPC classification number: G06F9/4403

Abstract: A memory initialization method for a plurality of memories. The memories are initialized according to predetermined initial parameters. A first quantity of the memories is detected. Optimum parameters are set according hardware information of the memories. The memories are re-initialized according to the optimum parameters. A second quantity of the memories is detected. The parameters for memory initialization are adjusted when the first quantity and the second quantity are different.

Abstract translation: 一种用于多个存储器的存储器初始化方法。 存储器根据预定的初始参数被初始化。 检测第一数量的存储器。 根据存储器的硬件​​信息设置最佳参数。 根据最佳参数重新初始化存储器。 检测到第二数量的存储器。 当第一数量和第二数量不同时，调整存储器初始化的参数。