公开(公告)号：US10305671B2

公开(公告)日：2019-05-28

申请号：US15159760

申请日：2016-05-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Bhoodev Kumar ,  Muraleedharan Ramakrishnan ,  Vivek Oppula ,  Thomas Hoff ,  Willem Zwart

IPC: H04L12/40 ,  H04L7/00 ,  G06F13/40 ,  G06F13/42

Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.