公开(公告)号：US10128828B2

公开(公告)日：2018-11-13

申请号：US15485062

申请日：2017-04-11

Applicant: Cirrus Logic International Semiconductor, Ltd.

Inventor： Muraleedharan Ramakrishnan ,  Bhoodev Kumar ,  Vivek Oppula ,  Niju Alex Geevarughese

IPC: H03L7/00 ,  H03K5/26

Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

公开(公告)号：US20170310315A1

公开(公告)日：2017-10-26

申请号：US15485062

申请日：2017-04-11

Applicant: Cirrus Logic International Semiconductor, Ltd.

Inventor： Muraleedharan Ramakrishnan ,  Bhoodev Kumar ,  Vivek Oppula ,  Niju Alex Geevarughese

IPC: H03K5/26

CPC classification number: H03K5/26

Abstract: A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

公开(公告)号：US20160344536A1

公开(公告)日：2016-11-24

申请号：US15159760

申请日：2016-05-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Bhoodev Kumar ,  Muraleedharan Ramakrishnan ,  Vivek Oppula ,  Thomas Hoff ,  Willem Zwart

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  G06F13/40 ,  G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

Abstract translation: 可以通过主设备和从设备之间的有线连接在通信路径上执行同步差分信令，以提供高带宽和/或低延迟通信。 可以通过提供可配置的帧结构在信令协议中提供灵活性。 灵活性可以在数据流映射到帧中的位时隙，改变下行链路和上行链路时隙数量，配置多个周转时间以及帧内周转的位置，配置控制字位（CWB）的位置和数量的情况下， 时隙，和/或调整通信链路的时钟频率。

公开(公告)号：US10305671B2

公开(公告)日：2019-05-28

申请号：US15159760

申请日：2016-05-19

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Bhoodev Kumar ,  Muraleedharan Ramakrishnan ,  Vivek Oppula ,  Thomas Hoff ,  Willem Zwart

IPC: H04L12/40 ,  H04L7/00 ,  G06F13/40 ,  G06F13/42

Abstract: Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.