Transfer for control data over half-duplex link

    公开(公告)号:US09946672B2

    公开(公告)日:2018-04-17

    申请号:US14838888

    申请日:2015-08-28

    Inventor: Willem Zwart

    CPC classification number: G06F13/36 G06F13/405 G06F13/4068 G06F13/4256

    Abstract: A method of transferring control data between a master device and a slave device over a path including at least one intermediate device, such that the path includes multiple path segments between successive pairs of devices. Data is transferred on each path segment in a plurality of frames of data, wherein the frames are synchronized between said path segments. The control data is transmitted in command slots of each frame, wherein a command slot comprises a set of control data bit slots, and wherein a control data bit slot is a time window associated with the transfer of a single control data bit over a single path segment between the devices on the path segment. The control data bit slots for each command slot are subdivided into: a first set of bit slots reserved for the transfer of control data in the direction from the master device to the slave device, and a second set of bit slots reserved for the transfer of control data either in the direction from the master device to the slave device or in the direction from the slave device to the master device. The time positions of the command slots on each path segment are offset from the positions of the command slots on each respective adjacent path segment by at least one control data bit slot.

    TRANSFER FOR CONTROL DATA OVER HALF-DUPLEX LINK
    3.
    发明申请
    TRANSFER FOR CONTROL DATA OVER HALF-DUPLEX LINK 有权
    通过双向链路传输控制数据

    公开(公告)号:US20170060794A1

    公开(公告)日:2017-03-02

    申请号:US14838888

    申请日:2015-08-28

    Inventor: Willem Zwart

    CPC classification number: G06F13/36 G06F13/405 G06F13/4068 G06F13/4256

    Abstract: A method of transferring control data between a master device and a slave device over a path including at least one intermediate device, such that the path includes multiple path segments between successive pairs of devices. Data is transferred on each path segment in a plurality of frames of data, wherein the frames are synchronized between said path segments. The control data is transmitted in command slots of each frame, wherein a command slot comprises a set of control data bit slots, and wherein a control data bit slot is a time window associated with the transfer of a single control data bit over a single path segment between the devices on the path segment. The control data bit slots for each command slot are subdivided into: a first set of bit slots reserved for the transfer of control data in the direction from the master device to the slave device, and a second set of bit slots reserved for the transfer of control data either in the direction from the master device to the slave device or in the direction from the slave device to the master device. The time positions of the command slots on each path segment are offset from the positions of the command slots on each respective adjacent path segment by at least one control data bit slot.

    Abstract translation: 一种通过包括至少一个中间设备的路径在主设备和从设备之间传送控制数据的方法,使得该路径包括连续的设备对之间的多个路径段。 在多个数据帧中的每个路径段上传送数据,其中帧在所述路径段之间同步。 控制数据在每个帧的命令时隙中发送,其中命令时隙包括一组控制数据位时隙,并且其中控制数据位时隙是与通过单个路径传送单个控制数据位相关的时间窗 路径段上的设备之间的段。 用于每个命令时隙的控制数据位时隙被细分为:保留用于在从主设备到从设备的方向上传送控制数据的第一组位时隙,以及保留用于传送 在从主设备到从设备的方向或从从设备到主设备的方向上控制数据。 每个路径段上的命令时隙的时间位置由每个相应的相邻路径段上的命令时隙的位置偏移至少一个控制数据位时隙。

    DIGITAL ACCESSORY INTERFACE
    4.
    发明申请
    DIGITAL ACCESSORY INTERFACE 有权
    数字附件界面

    公开(公告)号:US20170019244A1

    公开(公告)日:2017-01-19

    申请号:US14928179

    申请日:2015-10-30

    Inventor: Willem Zwart

    CPC classification number: H04L5/16 H04L7/0008

    Abstract: A method for transferring data over a half-duplex wired communications link, comprises, in each of a plurality of frames: transferring a synchronization data pattern in a first direction; transferring first payload data in the first direction; transferring second payload data in a second direction opposite to the first direction; and transferring control data, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

    Abstract translation: 一种通过半双工有线通信链路在设备之间传送数据的方法包括:在多个帧中的每一个中,沿第一方向传送同步数据模式,在第一方向上传送第一有效载荷数据, 第二方向与第一方向相反,并且传送控制数据。 帧的格式使得无论控制数据是在第一方向还是在第二方向上传送,在每帧中只有一对数据传送方向的反转。 通过这样约束同步符号,控制符号和有效载荷数据的顺序上升和下降,单个符号时隙可能足以适应设备之间的最大传输延迟并重新返回,以便在改变传输方向时可以避免开销或死区时间 。

    Low power bidirectional bus
    7.
    发明授权

    公开(公告)号:US10218535B2

    公开(公告)日:2019-02-26

    申请号:US15898839

    申请日:2018-02-19

    Abstract: A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.

    Digital accessory interface
    8.
    发明授权

    公开(公告)号:US09900143B2

    公开(公告)日:2018-02-20

    申请号:US14928382

    申请日:2015-10-30

    Inventor: Willem Zwart

    CPC classification number: H04L5/16 H04B3/02 H04L1/0061 H04L7/0008

    Abstract: A method is used for transferring data over a half-duplex wired communications link, wherein the wired communications link comprises first and second wires. The method comprises, in each of a plurality of frames: transferring a clock signal on the first wire in a first direction; transferring first payload data on the second wire in the first direction; transferring second payload data on the second wire in a second direction opposite to the first direction; and transferring control data on the second wire, wherein the format of the frame is such that, irrespective of whether the control data is transferred in the first direction or in the second direction, there is only one pair of reversals of a direction of data transfer in each frame.

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