-
公开(公告)号:US20240288477A1
公开(公告)日:2024-08-29
申请号:US18533477
申请日:2023-12-08
Inventor: Alastair M. BOOMER , John B. BOWLERWELL , Malcolm BLYTH , Eric J. KING
CPC classification number: G01R21/06 , G01R31/2837 , H02H7/20
Abstract: A system for estimating power dissipation in an integrated circuit comprising a power converter and an amplifier, the system comprising processing circuitry configured to: receive a signal indicative of an output voltage to a load which, in use of the integrated circuit, is driven by the amplifier; receive a signal indicative of an output current to the load; determine an output power value based on the received signal indicative of the output voltage to the load and the received signal indicative of the output current to the load; receive a signal indicative of an input voltage to the power converter; receive a signal indicative of an average current input to the power converter; determine an input power value based on the received signal indicative of the input voltage to the power converter and the received signal indicative of the average current input to the power converter; and determine a power dissipation value based on the determined output power value and the determined input power value.
-
公开(公告)号:US20240266948A1
公开(公告)日:2024-08-08
申请号:US18415208
申请日:2024-01-17
Inventor: John B. BOWLERWELL , Eric J. KING , Alastair M. BOOMER , Malcolm BLYTH
CPC classification number: H02M1/327 , H01L23/34 , H02M1/0009 , H02M3/156
Abstract: A method for controlling an input current limit of boost converter circuitry, the method comprising: receiving a power dissipation value for the boost converter circuitry; and controlling an input current limit of the boost converter circuitry based on the power dissipation value.
-
公开(公告)号:US20240097633A1
公开(公告)日:2024-03-21
申请号:US18521667
申请日:2023-11-28
Inventor: David P. SINGLETON , Andrew J. HOWLETT , John B. BOWLERWELL
IPC: H03F3/45
CPC classification number: H03F3/45659 , H03F3/45179 , H03F3/45645 , H03F2200/03 , H03F2203/45084 , H03F2203/45402 , H03F2203/45592
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
-
公开(公告)号:US20230198396A1
公开(公告)日:2023-06-22
申请号:US17699269
申请日:2022-03-21
Inventor: John B. BOWLERWELL , Alastair M. BOOMER , Holger HAIPLIK , Malcolm BLYTH
CPC classification number: H02M3/158 , G01R27/2611 , H02M1/0009
Abstract: Circuitry for estimating an inductance of an inductor in power converter circuitry, the circuitry comprising: circuitry for generating a peak inductor current signal indicative of a peak inductor current during an operational cycle of the power converter circuitry; circuitry for generating a ripple current estimate signal, indicative of an estimate of a ripple current in the power converter circuitry; and circuitry for applying the ripple current estimate signal to the peak inductor current signal to generate an average inductor current threshold signal indicative of an estimated average inductor current in the power converter circuitry during the operational cycle, wherein the ripple current estimate signal is based on: a duration of a charging phase of operation of the power converter circuitry; a voltage across the inductor; and an inductance value for the inductor; and wherein the circuitry for generating the ripple current estimate signal is operative to select an inductance value for the inductor for which the estimated average inductor current is equal to an actual average inductor current during the operational cycle to generate a value for the actual inductance of the inductor.
-
公开(公告)号:US20210232165A1
公开(公告)日:2021-07-29
申请号:US17140754
申请日:2021-01-04
Inventor: John B. BOWLERWELL , Andrew J. HOWLETT , Graeme S. ANGUS , Andrei DUMITRIU
Abstract: The present disclosure relates to circuitry for selecting a bias voltage to output at a bias voltage output node of the circuitry. The circuitry comprises a first circuit node configured to receive a first voltage from a first, unregulated, voltage source and a second circuit node configured to receive a second voltage from a second, regulated, voltage source. A switch arrangement configured to selectively couple the bias voltage output node to the first circuit node or the second circuit node is also provided.
-
-
-
-