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公开(公告)号：US20210273646A1
公开(公告)日：2021-09-02
申请号：US17184295
申请日：2021-02-24
Inventor： Andrew J. HOWLETT , David P. SINGLETON , Aniruddha SATOSKAR
Abstract: This application relates to ADC circuitry. An ADC circuit (200) has first and second conversion paths (201a, 201b) for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes (202a, 202b) to receive and convert full scale first and second analogue input signals (Ain1, Ain2) to separate digital outputs (Dout1, Dout2). In the second mode, the first and second conversion paths are both connected to the first input node (202a), to convert the first analogue input signal (Ain1) to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector (207) select the first digital signal or the second digital to be output as an output signal based on an indication of amplitude of the first analogue input signal.
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公开(公告)号：US20230299575A1
公开(公告)日：2023-09-21
申请号：US18183817
申请日：2023-03-14
Inventor： David P. SINGLETON , Andrew J. HOWLETT , Sharjeel RIAZ , John B. BOWLERWELL
CPC classification number: H02H7/20 , H02H1/0007
Abstract: An integrated circuit (IC), comprising: a converter comprising: one or more core devices; and one or more output internal nodes, each internal node coupled to one of the one or more core devices; protection circuitry comprising: one or more isolation switches, each of the one or more isolation switches coupled between a respective one of the one or more internal output nodes and a respective output external pin of the IC, wherein the protection circuitry configured to: monitor a characteristic at each respective external output pin of the IC; and if the characteristic is outside an operating specification of the one or more core devices, open one or more of the one or more isolation switches to isolate one or more of the one or more core devices from the respective external pin of the IC.
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公开(公告)号：US20210242847A1
公开(公告)日：2021-08-05
申请号：US17142904
申请日：2021-01-06
Inventor： David P. SINGLETON , Andrew J. HOWLETT , John B. BOWLERWELL
IPC: H03F3/45
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
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Patent Agency Ranking
公开(公告)号：US20230170850A1
公开(公告)日：2023-06-01
申请号：US17537619
申请日：2021-11-30
Inventor： Johnny KLARENBEEK , David P. SINGLETON , Morgan T. PRIOR , Jonathan T. WIGNER , Christopher M. DOUGHERTY , Qi CAI , Anindya BHATTACHARYA
CPC classification number: H03F1/0233 , H03F3/217 , H03F2200/03 , H03F2200/105
Abstract: Class D amplifier circuitry comprising: input buffer circuitry configured to receive a first digital input signal modulated according to a first modulation scheme in which the digital input signal can take a first plurality N of discrete signal levels; analog modulator circuitry configured to generate an analog modulated signal based on an analog output signal output by the input buffer circuitry; and quantizer circuitry configured to generate an output signal based on the analog modulated signal, wherein the output signal is modulated according to a second modulation scheme in which the output signal can take a second plurality M of discrete signal levels, wherein the second plurality M is greater than the first plurality N.
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公开(公告)号：US20220278658A1
公开(公告)日：2022-09-01
申请号：US17186741
申请日：2021-02-26
Inventor： John P. LESSO , David P. SINGLETON
Abstract: Class D amplifier circuitry comprising: modulator circuitry; and output stage circuitry, wherein the modulator circuitry is configured to: receive an input signal and first and second carrier signals, wherein the second carrier signal is offset in amplitude with respect to the first carrier signal; generate first and second modulated output signals, each of the first and second modulated output signals being based on the input signal and the first and second carrier signals; and generate a plurality of control signals for the output stage circuitry per signal period of the modulated output signals, wherein the plurality of control signals are based on the first and second modulated output signals, and wherein at least one of the plurality of control signals per signal period comprises a signal level transition.
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公开(公告)号：US20240154592A1
公开(公告)日：2024-05-09
申请号：US18505734
申请日：2023-11-09
Inventor： Andrew J. HOWLETT , Michael CHANDLER-PAGE , David P. SINGLETON , Erich P. ZWYSSIG , Craig MCADAM
CPC classification number: H03G3/30 , H03F3/04 , H03G2201/103
Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.
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公开(公告)号：US20240097633A1
公开(公告)日：2024-03-21
申请号：US18521667
申请日：2023-11-28
Inventor： David P. SINGLETON , Andrew J. HOWLETT , John B. BOWLERWELL
IPC: H03F3/45
CPC classification number: H03F3/45659 , H03F3/45179 , H03F3/45645 , H03F2200/03 , H03F2203/45084 , H03F2203/45402 , H03F2203/45592
Abstract: The present disclosure relates to circuitry comprising audio amplifier circuitry for receiving an audio signal to be amplified; and first and second output nodes for outputting first and second differential output signals. The circuitry further comprises common mode buffer circuitry configured to receive a common mode voltage and to selectively output the common mode voltage to the first and second output nodes.
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公开(公告)号：US20230353111A1
公开(公告)日：2023-11-02
申请号：US17982864
申请日：2022-11-08
Inventor： Andrew J. HOWLETT , Michael CHANDLER-PAGE , David P. SINGLETON , Erich P. ZWYSSIG
CPC classification number: H03G3/30 , H03F3/04 , H03G2201/103
Abstract: An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.
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