公开(公告)号：US12080630B2

公开(公告)日：2024-09-03

申请号：US18534433

申请日：2023-12-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

CPC classification number: H01L23/481 ,  H01L21/743 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/1066 ,  H01L29/66272 ,  H01L29/66704 ,  H01L29/66825 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/808 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H01L27/0623 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/16152 ,  H10B63/30 ,  H10B63/845

Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.

公开(公告)号：US12074079B2

公开(公告)日：2024-08-27

申请号：US17201468

申请日：2021-03-15

Applicant: Wolfspeed, Inc.

Inventor： Joohyung Kim ,  Sei-Hyung Ryu ,  Kijeong Han ,  Thomas E. Harrington, III ,  Edward Robert Van Brunt

IPC: H01L23/34 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L23/34 ,  H01L29/0696 ,  H01L29/7811 ,  H01L2924/3025

Abstract: Shielding techniques are used to provide an embedded sensor element such as a temperature sensing element on a wide bandgap power semiconductor device. A semiconductor device may include a drift layer and an embedded sensor element. The drift layer may be a wide bandgap semiconductor material. A shielding structure is provided in the drift layer below the embedded sensor element. The embedded sensor element may be provided between contacts that are in electrical contact with the shielding well. The distance between the contacts may be minimized. A noise reduction well may be provided between the contacts to further isolate the embedded sensor element from parasitic signals.

公开(公告)号：US12062655B2

公开(公告)日：2024-08-13

申请号：US17615390

申请日：2020-05-21

Applicant: ROHM CO., LTD.

Inventor： Jun Takaoka

IPC: H01L27/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/66 ,  H01L23/34 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L27/0664 ,  H01L21/26513 ,  H01L21/266 ,  H01L22/12 ,  H01L22/32 ,  H01L23/34 ,  H01L29/66348 ,  H01L29/7397

Abstract: A method for manufacturing a semiconductor device is provided in which a semiconductor element that generates heat during operation is formed in an active region of a semiconductor substrate and a temperature sensitive diode sensor arranged to detect temperature is formed in a temperature sensitive diode region of the semiconductor substrate. The method includes: forming a polysilicon layer that composes the temperature sensitive diode sensor in the temperature sensitive diode region, forming a mask, and introducing impurities through the mask into the semiconductor substrate and the polysilicon layer. The mask has an element pattern having an element opening through which a region composing the semiconductor element is exposed in the active region, a diode pattern having a diode opening through which a portion of the temperature sensitive diode region is exposed, and a monitoring pattern provided within the diode pattern with a size smaller than that of the diode opening.

公开(公告)号：US20240249991A1

公开(公告)日：2024-07-25

申请号：US18156779

申请日：2023-01-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hsiang Chen ,  Hsiu-Wen Hsueh ,  Szu-Lin Liu ,  Wen-Sheh Huang ,  Chloe Hsin-Yi Chen ,  Wei-Lin Lai

IPC: H01L23/34 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/34 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/5283

Abstract: A semiconductor structure includes a substrate having a front side and a back side, one or more dielectric layers over the front side, and a conductive structure. The one or more dielectric layers include a thermal sensor region and two dummy regions sandwiching the thermal sensor region along a second direction from a top view. The thermal sensor region and the two dummy regions extend longitudinally along a first direction generally perpendicular to the second direction from the top view. The conductive structure is embedded in the thermal sensor region of the one or more dielectric layers. The conductive structure includes conductive lines parallel to each other and extending longitudinally along the first direction, and conductive bars and vias electrically connecting the conductive lines. The conductive lines in a same dielectric layer of the one or more dielectric layers are electrically connected one by one zigzaggedly from the top view.

公开(公告)号：US20240249989A1

公开(公告)日：2024-07-25

申请号：US18158090

申请日：2023-01-23

Applicant: Apple Inc.

Inventor： Wei Chen ,  Balaji Nandhivaram Muthuraman ,  Arun Sasi ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Jun Zhai ,  Dominic Morache ,  Young Doo Jeon

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L23/3157 ,  H01L23/34 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/17055 ,  H01L2924/10162 ,  H01L2924/1811 ,  H01L2924/182

Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.

公开(公告)号：US20240203850A1

公开(公告)日：2024-06-20

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun KIM ,  Minjun BAE ,  Hyeonseok LEE ,  Gwangjae JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L25/18

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20240170376A1

公开(公告)日：2024-05-23

申请号：US18495043

申请日：2023-10-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kensuke MATSUZAWA ,  Taisuke FUKUDA

IPC: H01L23/495 ,  H01L23/34

CPC classification number: H01L23/49575 ,  H01L23/34 ,  H01L23/49531 ,  H01L24/48 ,  H01L2224/48225

Abstract: A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.

公开(公告)号：US11972996B2

公开(公告)日：2024-04-30

申请号：US17252287

申请日：2020-08-28

Applicant: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.

Inventor： Hang Liao ,  Qingyuan He ,  Chunhua Zhou

IPC: H01L23/34 ,  H01C7/02 ,  H01C7/04 ,  H01C17/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/34 ,  H01C7/02 ,  H01C7/04 ,  H01C17/00 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode, the second electrode and the gate structure are disposed on the second nitride semiconductor layer. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

公开(公告)号：US20240128162A1

公开(公告)日：2024-04-18

申请号：US18397906

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Ravindranath MAHAJAN ,  Debendra MALLIK ,  Sujit SHARAN ,  Digvijay RAORANE

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11955398B2

公开(公告)日：2024-04-09

申请号：US17354110

申请日：2021-06-22

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Eri Ogawa

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/66 ,  H01L23/00 ,  H01L23/043 ,  H01L23/34 ,  H01L23/373 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L21/4817 ,  H01L21/4871 ,  H01L22/12 ,  H01L23/043 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2224/40225 ,  H01L2224/73263 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1067 ,  H01L2924/12036 ,  H01L2924/1302 ,  H01L2924/13032 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/1715

Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.