公开(公告)号：US09985587B2

公开(公告)日：2018-05-29

申请号：US15168680

申请日：2016-05-31

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Zhaohui He ,  Eric J. King ,  Siddharth Maru ,  John L. Melanson

IPC: H03F3/217 ,  H03F1/32 ,  H03F3/183 ,  H03F3/45 ,  H04R3/00 ,  H03F1/02

CPC classification number: H03F1/32 ,  H03F1/0211 ,  H03F1/0227 ,  H03F1/0244 ,  H03F3/183 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/45076 ,  H03F2200/03 ,  H03F2203/45034 ,  H04R3/00 ,  H04R2420/03

Abstract: A switching power stage for producing a load voltage at a load output of the switching power stage, wherein the load output comprises a first load terminal having a first load voltage and a second load terminal having a second load voltage such that the load voltage comprises a difference between the first and the second load voltages, that may include: a power converter comprising a power inductor and a plurality of switches, wherein the power converter is configured to drive a power converter output terminal; a linear amplifier configured to drive a linear amplifier output terminal; and a controller for controlling the plurality of switches and the linear amplifier in order to generate the load voltage as a function of an input signal to the controller such that energy delivered to the load output is supplied predominantly by the power converter.

公开(公告)号：US09929664B2

公开(公告)日：2018-03-27

申请号：US15282790

申请日：2016-09-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Eric J. King ,  Zhaohui He ,  Siddharth Maru ,  John L. Melanson

IPC: H02M3/158 ,  H02M5/293

CPC classification number: H03F3/2171 ,  H02M5/293 ,  H02M2005/2932 ,  H03F1/0216 ,  H03F1/0227 ,  H03F1/32 ,  H03F3/185 ,  H03F3/2173 ,  H03F3/2178 ,  H03F2200/03 ,  H03F2200/153 ,  H03F2200/432 ,  H04R3/12

Abstract: A method may include controlling switches of a switching full-bridge of a signal processing system to commutate polarity of a capacitor with respect to the first processing path output and a second processing path output of the signal processing system in response to a condition for commutating connectivity of the switching full-bridge and inserting a feedforward compensation that bypasses a loop filter of the second processing path in order to prevent discontinuities caused by commutating polarity of the capacitor from being compensated by the loop filter.