公开(公告)号：US20200026993A1

公开(公告)日：2020-01-23

申请号：US16449932

申请日：2019-06-24

Applicant: DENSO CORPORATION

Inventor： Shigeki OTSUKA

IPC: G06N3/063 ,  G06N3/04 ,  H03M1/66 ,  H01L45/00 ,  G11C11/54 ,  G11C13/00

Abstract: A neural network circuit includes: multiple storage portions that include a memristor; multiple D/A converters that receive data, causing a signal voltage to be applied to multiple voltage input terminals of the storage portions; multiple drive amplifiers that are connected between to the D/A converters and the voltage input terminals; multiple I/V conversion amplifiers that are connected to at least one current output terminal of the storage portions; multiple A/D converters; and a series circuit of a first switch and a second switch that is disposed in a feedback loop of each of the drive amplifiers; and a series circuit of a third switch and a fourth switch that is disposed in a feedback loop of each of the I/V conversion amplifiers.

公开(公告)号：US20190332927A1

公开(公告)日：2019-10-31

申请号：US16379355

申请日：2019-04-09

Applicant: DENSO CORPORATION

Inventor： Shigeki OTSUKA ,  Irina KATAEVA

IPC: G06N3/063 ,  H03M1/46

Abstract: A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.

公开(公告)号：US20180331674A1

公开(公告)日：2018-11-15

申请号：US15775850

申请日：2016-11-11

Applicant: DENSO CORPORATION

Inventor： Takasuke ITO ,  Shigeki OTSUKA ,  Kazuyoshi NAGASE

IPC: H03H17/02 ,  H04B3/20

CPC classification number: H03H17/028 ,  H03H7/01 ,  H03H17/02 ,  H03H17/0248 ,  H04B3/04 ,  H04B3/20

Abstract: A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter.