公开(公告)号：US10164610B2

公开(公告)日：2018-12-25

申请号：US15775850

申请日：2016-11-11

Applicant: DENSO CORPORATION

Inventor： Takasuke Ito ,  Shigeki Otsuka ,  Kazuyoshi Nagase

IPC: H03H17/02 ,  H04B3/20

Abstract: A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter.

公开(公告)号：US12026608B2

公开(公告)日：2024-07-02

申请号：US16710296

申请日：2019-12-11

Applicant: DENSO CORPORATION

Inventor： Irina Kataeva ,  Shigeki Otsuka

IPC: G06N3/06 ,  G06N3/065 ,  G06N3/08 ,  G06N3/084 ,  G06N5/046 ,  G06N20/00 ,  G11C11/40 ,  G11C11/54

CPC classification number: G06N3/065 ,  G06N3/084 ,  G06N5/046 ,  G06N20/00 ,  G11C11/40 ,  G11C11/54

Abstract: A method for adjusting output level of a neuron in a multilayer neural network is provided. The multilayer neural network includes a memristor and an analog processing circuit, causing transmission of the signals between the neurons and the signal processing in the neurons to be performed in an analog region. The method includes an adjustment step that adjusts an output level of the neurons of each of the layers, causing the output value to become lower than a write threshold voltage of the memristor and to fall within a maximum output range set for the analog processing circuit executing the generation of the output value in accordance with the activation function when each of the output values of the neurons of each of the layers becomes highest.

公开(公告)号：US11501146B2

公开(公告)日：2022-11-15

申请号：US16731667

申请日：2019-12-31

Applicant: DENSO CORPORATION

Inventor： Irina Kataeva ,  Shigeki Otsuka

IPC: G06N3/063 ,  G06N3/04 ,  G06T9/00

Abstract: A image recognition system includes a first convolution layer, a pooling layer, a second convolution layer, a crossbar circuit having a plurality of input lines, at least one output line intersecting with the input lines, and a plurality of weight elements that are provided at intersection points between the input lines and the output line, weights each input value input to the input lines to output to the output line, and a control portion that selects from convolution operation results of the first convolution layer, an input value needed to acquire each pooling operation result needed to perform second filter convolution operation at each shift position in the second convolution layer, and inputs the input value selected to the input lines.

公开(公告)号：US10943170B2

公开(公告)日：2021-03-09

申请号：US16249190

申请日：2019-01-16

Applicant: DENSO CORPORATION

Inventor： Shigeki Otsuka ,  Hironobu Akita ,  Irina Kataeva

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/54 ,  G11C13/00

Abstract: A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.

公开(公告)号：US11928576B2

公开(公告)日：2024-03-12

申请号：US16654394

申请日：2019-10-16

Applicant: DENSO CORPORATION

Inventor： Irina Kataeva ,  Shigeki Otsuka

IPC: G06N3/063 ,  G06F11/30 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F11/3058 ,  G06N3/08

Abstract: The present disclosure describes an artificial neural network circuit including: at least one crossbar circuit to transmit a signal between layered neurons of an artificial neural network, the crossbar circuit including multiple input bars, multiple output bars arranged intersecting the input bars, and multiple memristors that are disposed at respective intersections of the input bars and the output bars to give a weight to the signal to be transmitted; a processing circuit to calculate a sum of signals flowing into each of the output bars while a weight to a corresponding signal is given by each of the memristors; a temperature sensor to detect environmental temperature; and an update portion that updates a trained value used in the crossbar circuit and/or the processing circuit.

公开(公告)号：US11831471B2

公开(公告)日：2023-11-28

申请号：US17841030

申请日：2022-06-15

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Shigeki Otsuka ,  Hyoungjun Na ,  Takasuke Ito ,  Yoshikazu Furuta ,  Tomohiro Nezuka

IPC: H04L25/02 ,  H04B3/56

CPC classification number: H04L25/0272 ,  H04B3/56 ,  H04L25/0278

Abstract: A differential communication circuit is connected to a communication line formed of a positive communication line and a negative communication line for differential communication. The differential communication circuit includes: a series circuit that includes a resistor element and a connection switch. The resistor element is connected between the positive and negative communication lines when the connection switch is turned on. The circuit also includes a transmission unit that is configured to output a differential signal to the communication line and a controller that is configured to change impedance of the communication line by turning on the connection switch in a period during which the transmission unit does not output the differential signal.

公开(公告)号：US11475272B2

公开(公告)日：2022-10-18

申请号：US16562534

申请日：2019-09-06

Applicant: DENSO CORPORATION

Inventor： Shigeki Otsuka

IPC: G06N3/063 ,  G06N3/06 ,  G11C13/00 ,  G11C11/54 ,  G06N3/04 ,  G06F7/544 ,  H03F3/45

Abstract: A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage application device arranged to apply a bias voltage to the memory device and current-voltage (I-V) conversion amplification circuits arranged to convert currents flowing via the memory elements into voltages and output the voltage. A feedback resistor of a respective I-V conversion amplification circuit includes a memristor. The feedback resistor of a respective I-V conversion amplification circuit and the memory elements acting as an input resistor of the I-V conversion amplification circuit are connected to align a polarity direction of the memristor of the feedback resistor and polarity directions of the memristors of the memory elements acting as the input resistor.