公开(公告)号：US09240728B2

公开(公告)日：2016-01-19

申请号：US14459159

申请日：2014-08-13

Applicant: DORA S.p.A.

Inventor： Alberto Iorio ,  Maurizio Foresta ,  Alberto Bianco

IPC: H02M3/335 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M3/33576 ,  H02M3/1588 ,  H02M3/33592 ,  H02M2001/0058 ,  Y02B70/1425 ,  Y02B70/1433 ,  Y02B70/1466 ,  Y02B70/1475 ,  Y02B70/1491

Abstract: A control device detects zero crossings of a current through a rectifier transistor during plural cycles; generates a turn-on signal of the transistor and inserts a turn-on delay equal to a fixed first quantity from the start time of for each cycle. The control device starts counting consecutive cycles after inserting the turn-on delay; detects whether a zero crossing of the current through the transistor after turning on said transistor has occurred; if no zero crossing is detected before counting a number N of consecutive cycles, decreases the turn-on delay by a fixed second quantity for the next cycle; if a zero crossing is detected, maintains turned on the transistor; if the turn-on delay is smaller than first quantity, increases the turn-on delay o for the next switching cycle; and if the turn-on delay is equal to the first quantity, maintains the turn-on delay for the next switching cycle.

Abstract translation: 控制装置在多个周期期间检测通过整流器晶体管的电流的过零点; 产生晶体管的导通信号，并从每个周期的开始时间插入等于固定的第一量的导通延迟。 控制装置在插入接通延迟后开始连续循环计数; 检测在导通所述晶体管之后是否发生通过所述晶体管的电流的过零点; 如果在对连续循环数N进行计数之前没有检测到零交叉，则在下一个周期将导通延迟减少固定的第二数量; 如果检测到零交叉，维持导通晶体管; 如果导通延迟小于第一量，则增加下一个开关周期的导通延迟o; 并且如果导通延迟等于第一数量，则维持下一个开关周期的导通延迟。

公开(公告)号：US20130285634A1

公开(公告)日：2013-10-31

申请号：US13871809

申请日：2013-04-26

Applicant: DORA S.P.A.

Inventor： Alberto Bianco

IPC: H02M3/157

CPC classification number: H02M3/158 ,  H02M1/08 ,  H02M3/1563 ,  H02M3/157 ,  H02M2001/0025

Abstract: A control circuit for a switching voltage regulator is configured to receive an error signal representative of a regulator output voltage in relation to a nominal output voltage, and includes a set/reset flip-flop, a hysteresis comparator and a logic circuit. The flip-flop is configured to produce a switching control signal according to logic values at its set and reset terminals. The comparator is configured to produce a set signal at the set terminal when an error signal drops below a first value, and a reset signal when the error signal rises above a second value. The logic circuit is configured to prevent transmission of the reset signal to the reset terminal during a selected minimum time period and to thereafter enable transmission of the reset signal, and further, to produce an alternate reset signal at the reset terminal at the end of the selected maximum time period.

Abstract translation: 用于开关稳压器的控制电路被配置为接收代表与额定输出电压相关的调节器输出电压的误差信号，并且包括设置/复位触发器，迟滞比较器和逻辑电路。 触发器被配置为根据其设置和复位端子处的逻辑值产生开关控制信号。 比较器被配置为当误差信号低于第一值时在设定端产生设置信号，当误差信号上升到第二值以上时，产生复位信号。 逻辑电路被配置为在所选择的最小时间段期间防止复位信号传输到复位端，并且此后能够传输复位信号，并且进一步在复位端产生替代复位信号 选定的最大时间段。