公开(公告)号：US20200350350A1

公开(公告)日：2020-11-05

申请号：US16399806

申请日：2019-04-30

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H01L27/146 ,  H04N5/378 ,  H04N5/3745

摘要： A pixel includes a photodiode, a first transfer gate, a second transfer gate, and a floating diffusion. The pixel may include a storage gate, and the first transfer gate may be controllable to transfer charge from the photodiode to an area under the storage gate. The storage gate is controllable to store the charge in the area under the storage gate and to transfer the charge from the area under the storage gate. The first transfer gate may be controllable among a first biasing condition in which charge is transferable to an area under the first transfer gate, a second biasing condition in which the charge is storable in the area under the first transfer gate, and a third biasing condition in which the charge is transferable out of the area under the first transfer gate. The second transfer gate is controllable to transfer charge to the floating diffusion.

公开(公告)号：US10057523B1

公开(公告)日：2018-08-21

申请号：US15431567

申请日：2017-02-13

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H04N5/376 ,  H04N5/378 ,  H04N5/907

摘要： An image sensor includes a pixel array, a plurality of memory blocks, a plurality of phase-locked loops, and a plurality of serializers. The pixel array includes a plurality of pixels. The plurality of memory blocks store digital pixel data converted from analog pixel signals output from the pixel array, and are located to a particular side of the pixel array. The plurality of phase-locked loops are located to the particular side of the pixel array. The plurality of serializers are located to the particular side of the pixel array. Each serializer of the plurality of serializers is connected to receive parallel data input from one or more corresponding memory blocks of the plurality of memory blocks and is configured to convert the parallel data input to serial data output using a corresponding plurality of clock signals from a corresponding phase-locked loop of the plurality of phase-locked loops.

公开(公告)号：US09019411B2

公开(公告)日：2015-04-28

申请号：US13648067

申请日：2012-10-09

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H04N3/14 ,  H04N5/335 ,  H04N5/217 ,  H04N5/374 ,  H04N5/378

CPC分类号： H04N5/3742 ,  H04N5/378

摘要： A pipelined readout method in an image sensor includes receiving one or more signals from a pixel of a row of a pixel array into a column storage at least partially during a time that a previously sampled amplified output of the column storage that is based on signals provided by a previous pixel of a previously read out row of the pixel array is converted from analog to digital by an analog-to-digital conversion circuit. The method further includes performing, by the analog-to-digital conversion circuit, analog-to-digital conversion of a sampled amplified output of the column storage that is based on the one or more signals from the pixel at least partially during a time that the column storage receives at least one signal from a another pixel of a subsequently read out row of the pixel array.

摘要翻译： 图像传感器中的流水线读出方法包括：在基于所提供的信号的列存储器的先前采样的放大输出的时间期间至少部分地将一个或多个信号从像素阵列的像素的像素接收到列存储器中 由像素阵列的先前读出的行的先前像素通过模数转换电路从模拟转换成数字。 该方法还包括通过模数转换电路，在至少部分地在该时间期间，基于来自该像素的一个或多个信号，对列存储器的采样放大输出进行模数转换 列存储从像素阵列的随后读出的行的另一个像素接收至少一个信号。

公开(公告)号：US08785831B2

公开(公告)日：2014-07-22

申请号：US13343662

申请日：2012-01-04

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H01L27/00

CPC分类号： H04N5/378 ,  H01L27/14607 ,  H01L27/1461 ,  H04N5/3742 ,  H04N5/3745 ,  H04N5/37452

摘要： An image sensor includes a plurality of pixels and a row driver. Each pixel includes a photodiode, a first transfer gate, a second transfer gate, a first storage node, and a second storage node. The row driver is configured to provide signals to the first transfer gate and the second transfer gate of each pixel such that charge is transferred from the photodiode to the first storage node through the first transfer gate while a signal representing charge stored at the second storage node is output from the pixel to a column readout line. The row driver is also configured to provide signals to the first transfer gate and the second transfer gate such that charge is transferred from the photodiode to the second storage node through the second transfer gate while a signal representing charge stored at the first storage node is output from the pixel.

摘要翻译： 图像传感器包括多个像素和行驱动器。 每个像素包括光电二极管，第一传输门，第二传输门，第一存储节点和第二存储节点。 行驱动器被配置为向每个像素的第一传输门和第二传输门提供信号，使得电荷通过第一传输门从光电二极管传送到第一存储节点，同时表示存储在第二存储节点处的电荷的信号 从像素输出到列读出线。 行驱动器还被配置为向第一传输门和第二传输门提供信号，使得电荷通过第二传输门从光电二极管传送到第二存储节点，同时输出表示存储在第一存储节点处的电荷的信号 从像素。

公开(公告)号：US07986363B2

公开(公告)日：2011-07-26

申请号：US12155823

申请日：2008-06-10

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H04N5/335

CPC分类号： H04N5/235 ,  H04N5/2355 ,  H04N5/335

摘要： A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the imager are adapted to process pixel signals corresponding to the integration periods in parallel. The pixel signals are converted into digital values in parallel. The digital values are each linear functions of the incident light and therefore suitable for use with conventional color processing algorithms. A pipelined rolling shutter operation may be employed where the short integration period of one row of pixels is performed simultaneously with the long integration period of another row of pixels.

摘要翻译： 高动态范围成像器利用至少短的积分周期和长积分周期来操作像素。 成像器的像素读取电路适于并行处理对应于积分周期的像素信号。 像素信号被并行转换为数字值。 数字值是入射光的每个线性函数，因此适用于常规颜色处理算法。 可以采用流水线滚动快门操作，其中一行像素的短积分周期与另一行像素的长积分周期同时执行。

公开(公告)号：USRE41340E1

公开(公告)日：2010-05-18

申请号：US11524495

申请日：2006-09-21

申请人： Vladimir Berezin ,  Alexander Krymski ,  Eric R. Fossum

发明人： Vladimir Berezin ,  Alexander Krymski ,  Eric R. Fossum

IPC分类号： H01L31/101 ,  H01L31/062

CPC分类号： G01S7/487 ,  H01L27/14601 ,  H01L27/14609 ,  H01L27/14643

摘要： A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight. A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that share buffer transistors. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of a shared buffer transistor.

摘要翻译： 锁定光电二极管光电检测器的锁定器包括顺序启用的多个输出端口。 每当启用输出端口时，都被认为是不同的时间段。 发送指定的模式，并调查输出框以查找该模式。 接收到花样的时间表示飞行时间。 CMOS有源像素图像传感器包括共享缓冲晶体管的多个钉扎光电二极管光电检测器。 在一种配置中，来自两个或更多个被钉扎的光电二极管的电荷可以合并在一起并施加到共享缓冲晶体管的栅极。

公开(公告)号：US07659925B2

公开(公告)日：2010-02-09

申请号：US11243239

申请日：2005-10-04

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H04N5/228 ,  H04N3/14 ,  H04N5/335 ,  H01L27/00 ,  H03M1/12

CPC分类号： H04N5/32

摘要： An image sensor circuit includes a pixel array, a plurality of column analog-to-digital conversion (ADC) circuits, and at least two memory blocks. Each column ADC circuit is connected to receive analog pixel signals provided from corresponding pixel circuits of the pixel array, and is configured to convert the received analog pixel signals into digital pixel signals. Each memory block is connected to receive digital pixel signals provided from corresponding column ADC circuits of the plurality of column ADC circuits. At least two of the at least two memory blocks are connected to receive digital pixel signals that are provided from corresponding column ADC circuits that are located to a same side of the pixel array. Each memory block of the at least two memory blocks includes a plurality of memory cells, one or more sense amplifiers connected to the memory cells by a readout bus, and a memory controller.

摘要翻译： 图像传感器电路包括像素阵列，多个列模数转换（ADC）电路和至少两个存储器块。 每列ADC电路被连接以接收从像素阵列的相应像素电路提供的模拟像素信号，并且被配置为将接收到的模拟像素信号转换成数字像素信号。 每个存储块被连接以接收从多个列ADC电路的相应列ADC电路提供的数字像素信号。 连接至少两个存储器块中的至少两个以接收从位于像素阵列的同一侧的相应列ADC电路提供的数字像素信号。 所述至少两个存储器块的每个存储块包括多个存储器单元，通过读出总线连接到存储器单元的一个或多个感测放大器和存储器控制器。

公开(公告)号：US20090273500A1

公开(公告)日：2009-11-05

申请号：US12434602

申请日：2009-05-01

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H03M1/12

CPC分类号： H03M1/144 ,  H03M1/56

摘要： Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.

摘要翻译： 双路斜坡模数转换器和方法允许对模拟信号进行模数转换。 各种双斜坡模数转换器和方法允许将模拟信号和粗斜坡施加到比较器的相同输入端，以及向比较器的另一输入端施加精细斜坡。 一些双斜坡模数转换器和方法允许将模拟信号，粗斜坡和精细斜坡应用于比较器的相同输入。 各种双斜坡模数转换器和方法允许将模拟信号施加到第一比较器的输入，通过粗斜波开关将粗斜坡施加到第一比较器的输入端，将模拟信号施加到 第二比较器，并且向第二比较器的另一输入端施加精细斜坡。

公开(公告)号：US07400279B2

公开(公告)日：2008-07-15

申请号：US11777905

申请日：2007-07-13

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H03M1/06

CPC分类号： H03M1/0607

摘要： Circuits and methods may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section.

摘要翻译： 可以通过使用补偿比较器输入偏移对比较器决定的影响的ADC来改善电路和方法。 通过在ADC的输入端和ADC的比较器部分之间使用放大器部分放大提供给比较器输入的信号，从而减小比较器偏移对比较器判定的影响，可以在ADC中实现偏移补偿。 比较器部分可以是自动调零比较器部分，其能够执行偏移减小操作以在其输入处提供的电容器处存储偏移补偿值。 放大器部分可以是具有一个或多个放大器级的自动调零放大器部分，其能够执行偏移减小操作以在其输入处提供的电容器处存储偏移补偿值。 偏移补偿也可以使用没有前一放大器部分的自动调零比较器部分来实现。

公开(公告)号：US07319218B2

公开(公告)日：2008-01-15

申请号：US11601749

申请日：2006-11-20

申请人： Alexander Krymski

发明人： Alexander Krymski

IPC分类号： H01L27/00 ,  H04N5/217

CPC分类号： H04N5/347

摘要： A binning circuit and related method, wherein pixel signals from column circuits in a sensor circuit are sampled and interpolated. The binning circuit samples analog pixel and reset signals from different sensor circuit column lines. Once a predetermined number of column lines are sampled in the binning circuit, the sampled pixel signals are averaged together in one operation, while the reset signals are averaged together in another operation.

摘要翻译： 一种分级电路及相关方法，其中来自传感器电路中的列电路的像素信号被采样和内插。 分级电路对来自不同传感器电路列线的模拟像素和复位信号进行采样。 一旦在合并电路中对预定数量的列线进行采样，则在一次操作中采样像素信号被平均化，而在另一操作中复位信号被平均化。