Integrated circuit with improved current mirror impedance and method of operation
    11.
    发明授权
    Integrated circuit with improved current mirror impedance and method of operation 有权
    具有改善的电流镜阻抗的集成电路和操作方法

    公开(公告)号:US06362613B1

    公开(公告)日:2002-03-26

    申请号:US09711482

    申请日:2000-11-13

    Inventor: David Rodriguez

    CPC classification number: G05F3/262

    Abstract: An integrated circuit (200, 300, 500) includes a current mirror having high output impedance and also having an output device with a low drain-to-source saturation voltage.

    Abstract translation: 集成电路(200,300,500)包括具有高输出阻抗的电流镜,并且还具有具有低漏 - 源饱和电压的输出装置。

    System and method for reducing particles in epitaxial reactors
    12.
    发明授权
    System and method for reducing particles in epitaxial reactors 失效
    用于还原外延反应器中的颗粒的系统和方法

    公开(公告)号:US6161311A

    公开(公告)日:2000-12-19

    申请号:US113934

    申请日:1998-07-10

    Abstract: An apparatus and method for reducing particles in reactors. The apparatus includes an enclosure for processing the semiconductor wafers. The enclosure has a wafer handling chamber connected by an isolation gate valve to a processing chamber. Additionally, the apparatus includes pipes for delivering a purge gas into the wafer handling chamber. The purge gas is used to eliminates particles from the enclosure. The apparatus also includes a pilot operated back pressure regulator for regulating the delivery and removal of the purge gas from the enclosure. The apparatus actuates the isolation gate valve in a controlled rate to reduce disturbances from the purge gas entering into the enclosure. The apparatus also includes a Bernoulli wand for lifting and holding a single semiconductor wafer. A dome loaded regulator is used to control the ramp rates of the gas to the Bernoulli wand. The dome loaded regulator is actuated by a pilot gas. The ramp up and ramp down rates of the Bernoulli wand gas can be control by a multitude of restrictions and check valves in the pilot gas line. The apparatus also utilizes ionizers in the purge gas lines entering the wafer handling chamber and load locks. Through the use of an alpha particle emission source in the purge gas line prior to the load lock and wafer handling chamber, the purged gas molecules are ionized. The ionized gas is conductive and therefore discharges all static inside the semiconductor equipment. By removable of the static charge particle and wafers are no longer attracted to each other by electrostatic force. In addition, the apparatus includes means for reducing gas flow turbulence when switching valves within the reactor.

    Abstract translation: 用于还原反应器中的颗粒的装置和方法。 该装置包括用于处理半导体晶片的外壳。 外壳具有通过隔离闸阀连接到处理室的晶片处理室。 此外,该装置包括用于将清洗气体输送到晶片处理室中的管道。 净化气体用于消除外壳中的颗粒。 该设备还包括用于调节从外壳传送和去除净化气体的先导操作的后部压力调节器。 该设备以受控的速率驱动隔离闸阀,以减少进入外壳的吹扫气体的干扰。 该装置还包括用于提升和保持单个半导体晶片的伯努利棒。 使用圆顶加载的调节器来控制气体对伯努利棒的斜坡率。 圆顶式调压器由先导气体驱动。 伯努利魔杖气的升高和降速率可以通过大量限制和先导气体管路中的止回阀来控制。 该设备还在进入晶片处理室的清洗气体管线和负载锁定中使用电离器。 通过在负载锁定和晶片处理室之前在吹扫气体管线中使用α粒子发射源,将净化的气体分子电离。 电离气体是导电的,因此将半导体设备内的所有静电放电。 通过可移除的静电荷颗粒和晶片不再被静电力彼此吸引。 另外,该装置包括当在反应器内切换阀时减少气流湍流的装置。

    METHOD AND INSTALLATION FOR PRODUCING DIRECT REDUCED IRON
    15.
    发明申请
    METHOD AND INSTALLATION FOR PRODUCING DIRECT REDUCED IRON 审中-公开
    生产直接还原铁的方法和安装

    公开(公告)号:US20120031236A1

    公开(公告)日:2012-02-09

    申请号:US13262796

    申请日:2010-04-06

    Abstract: “A method for producing direct reduced iron in a vertical reactor having an upper reducing zone and a lower cooling zone, the method including: feeding iron oxide feed material to an upper portion of the vertical reactor, the iron oxide feed material forming a burden flowing by gravity to a material outlet portion in a lower portion of the vertical reactor; feeding hot reducing gas to a lower portion of the reducing zone of the vertical reactor, the hot reducing gas flowing in a counter flow to the burden towards a gas outlet port in the upper portion of the vertical reactor; recovering direct reduced iron at the lower portion of the vertical reactor; recovering top gas at the upper portion of the vertical reactor; submitting at least a portion of the recovered top gas to a recycling process; and feeding the recycled top gas back into the vertical reactor, where the recycling process includes heating the recovered top gas in a preheating unit before feeding it to a reformer unit; feeding volatile carbon containing material to the reformer unit and allowing the volatile carbon containing material to devolatise and to react with the recovered top gas; feeding desulfurizing agent into the recovered top gas in or upstream of the reformer unit; heating the reformer unit; and feeding the reformed top gas recovered from the reformer unit through a particle separation device for removal of sulfur containing material.”

    Abstract translation: “在具有上部还原区和下部冷却区的立式反应器中生产直接还原铁的方法,该方法包括:将铁氧化物进料输送到垂直反应器的上部,氧化铁原料形成流动的负荷 通过重力引导到垂直反应器的下部的材料出口部分; 将热还原气体供给到垂直反应器的还原区域的下部,热还原气体逆流流向垂直反应器上部的气体出口的负荷; 在垂直反应器的下部回收直接还原铁; 在垂直反应器的上部回收顶部气体; 将回收的顶部气体的至少一部分提交到再循环过程; 并将再循环的顶部气体送回到垂直反应器中,其中回收过程包括在将其送入重整器单元之前将预热单元中回收的顶部气体加热; 将含挥发性碳的材料供给重整单元,并使含挥发性碳的材料脱挥发和与回收的顶部气体反应; 将脱硫剂进料到重整器单元内或上游的回收顶部气体中; 加热重整单元; 并通过用于除去含硫物质的颗粒分离装置将从重整单元回收的重整顶部气体进料。

    METHOD OF THREE-DIMENSIONAL GRAPHICAL MODELLING
    16.
    发明申请
    METHOD OF THREE-DIMENSIONAL GRAPHICAL MODELLING 审中-公开
    三维图形建模方法

    公开(公告)号:US20100234972A1

    公开(公告)日:2010-09-16

    申请号:US12377742

    申请日:2007-07-27

    CPC classification number: G06F17/50 G06F2217/06 G06F2217/12 Y02P90/265

    Abstract: The invention relates to the field of methods of three-dimensional graphical modelling. This is a method of three-dimensional graphical modelling of an interface between several elements, comprising at least: for at least two elements, a step of determining one or more parameters of the element that relate to the interface; a step of displaying, at the level of a software resource, a three-dimensional graphical modelling of the interface with the aid of the parameters determined, at least one of the elements being a phase of a manufacturing method, at least one determined parameter of which used for the displaying step corresponds to a constraint imposed by the manufacturing method phase.

    Abstract translation: 本发明涉及三维图形建模方法领域。 这是几个元件之间的界面的三维图形建模的方法,至少包括:对于至少两个元件,确定与该界面相关的元件的一个或多个参数的步骤; 借助于所确定的参数在软件资源级别显示界面的三维图形建模的步骤,所述元件中的至少一个是制造方法的相位,至少一个确定的参数 用于显示步骤的步骤对应于制造方法阶段施加的约束。

    Pad ESD spreading technique
    17.
    发明授权
    Pad ESD spreading technique 有权
    垫ESD传播技术

    公开(公告)号:US07564665B2

    公开(公告)日:2009-07-21

    申请号:US11621724

    申请日:2007-01-10

    CPC classification number: H02H9/046

    Abstract: A system, e.g. an integrated circuit or part, may include a plurality of pads, e.g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

    Abstract translation: 系统,例如 集成电路或部件可以包括多个焊盘,例如, 数字I / O焊盘,每个包括物理焊盘和相关焊盘电路。 在影响一个或多个数字I / O焊盘的ESD事件的情况下,配置在I / O焊盘电源轨和物理输出焊盘之间的输出缓冲区中的PMOS器件在其受影响的数字I的各自的焊盘电路内 / O焊盘 - 可能会响应于ESD事件而打开。 这可以允许每个焊盘的电容,在一些情况下,每个焊盘约为3pF的电容充电,吸收ESD事件的能量并降低集成电路或部件作为ESD事件的结果所经历的峰值电压。 降低的峰值电压可以直接与产品的ESD性能相关。

    Semiconductor component comprising an electrostatic-discharge protection
device
    18.
    发明授权
    Semiconductor component comprising an electrostatic-discharge protection device 失效
    半导体元件包括静电放电保护器件

    公开(公告)号:US6040604A

    公开(公告)日:2000-03-21

    申请号:US897964

    申请日:1997-07-21

    CPC classification number: H01L23/60 H01L27/0248 H01L2924/0002 H01L2924/3011

    Abstract: A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers (21, 24, 27) between the interconnect layers (23, 26, 29) wherein a portion (48) of the top interconnect layer (29) overlies portions (47, 42, 43) of the underlying interconnect layers (23, 26) and wherein a portion (47) of the middle interconnect layer (26) does not overlie the portions (42, 43) of the bottom interconnect layer (23) and also does not overlie portions (32, 33) of one of the doped regions (20).

    Abstract translation: 半导体部件(10)包括衬底(11),衬底(11)中的掺杂区域(15,20),耦合到一个掺杂层的互连层(23,26,29)和介电层(21, 其中所述顶部互连层(29)的一部分(48)位于所述下部互连层(23,26)的部分(47,42,43)之间,并且其中,所述互连层(23,26,29) 中间互连层(26)的一部分(47)不覆盖在底部互连层(23)的部分(42,43)上,也不覆盖一个掺杂区域(20)的部分(32,33) )。

    Power-assisted upper extremity orthosis
    19.
    发明授权
    Power-assisted upper extremity orthosis 失效
    动力辅助上肢矫形器

    公开(公告)号:US5800561A

    公开(公告)日:1998-09-01

    申请号:US649967

    申请日:1996-05-15

    Inventor: David Rodriguez

    CPC classification number: A61F5/013

    Abstract: An orthotic device for a human forearm and hand is provided having first and second gripping members that are interposable between the thumb and fingers of a user's hand. An actuator moves one gripping member relative to the second gripping member in response to user input. The actuator of the orthotic device can include a gas piston driven by compressed gas. A valve controlling gas flow is actuated by an electric motor.

    Abstract translation: 提供了一种用于人类前臂和手的矫正装置,其具有可在使用者的手的拇指和手指之间插入的第一和第二夹持构件。 响应于用户的输入,致动器相对于第二夹持构件移动一个夹持构件。 矫正装置的致动器可以包括由压缩气体驱动的气体活塞。 控制气体流量的阀门由电动机驱动。

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