公开(公告)号：US08477831B2

公开(公告)日：2013-07-02

申请号：US12860482

申请日：2010-08-20

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04L27/06

CPC分类号： H04L5/1446 ,  H04L1/0002 ,  H04L1/0025

摘要： An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

摘要翻译： 用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分，可编程地配置为至少三个数据速率的接收机部分，以及可操作地连接到发射机部分和接收机部分的自动速度协商模块 配置发射机部分和接收机部分，以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。 可以通过调整发射机数据路径宽度和接收机数据路径宽度，调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。 可以使能或禁用字节序列化或反序列化，以根据数据速率改变数据的宽度，以传输到/从本地设备的其余部分。

公开(公告)号：US08788862B1

公开(公告)日：2014-07-22

申请号：US13175745

申请日：2011-07-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： G06F1/32

CPC分类号： G06F1/3278 ,  Y02D10/157 ,  Y02D50/20

摘要： A method and system for efficiently transitioning a communication circuit from a low-power state are disclosed. A first device and second device in a low-power state may be transitioned to an active state to enable the transmission of data over a communication link, where energy consumption of one or more components of the first and/or second devices may be reduced in the low-power state. The transition may be initiated by the first device responsive to a signal and/or an expiration of a timer. Responsive thereto, a scrambler of the first device may be temporarily bypassed to accelerate achieving block lock at the second device, thereby enabling the system to more quickly transition from the low-power state to the active state.

摘要翻译： 公开了一种将通信电路从低功率状态有效地转变的方法和系统。 处于低功率状态的第一设备和第二设备可以被转换到活动状态，以便能够通过通信链路传输数据，其中可以减少第一和/或第二设备中的一个或多个组件的能量消耗 低功耗状态。 第一设备可以响应于信号和/或定时器的期满而启动转换。 响应于此，第一设备的加扰器可能被暂时旁路以加速实现第二设备处的块锁定，从而使得系统能够更快地从低功率状态转换到活动状态。

公开(公告)号：US08732375B1

公开(公告)日：2014-05-20

申请号：US12752641

申请日：2010-04-01

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： G06F13/14

CPC分类号： G06F13/385

摘要： Structures and methods are disclosed relating to a multi-protocol transceiver including lane-based Physical Coding Sublayer (“PCS”) circuitry that is configurable to adapt to one of a plurality of communication protocols. Particular embodiments of the present invention include lane based configurable data paths through PCS transmit and receive circuitry.

摘要翻译： 公开了涉及包括基于通道的物理编码子层（“PCS”）电路的多协议收发器的结构和方法，该电路可配置为适应多个通信协议之一。 本发明的特定实施例包括通过PCS发送和接收电路的基于通道的可配置数据路径。

公开(公告)号：US20120307878A1

公开(公告)日：2012-12-06

申请号：US12860482

申请日：2010-08-20

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04B3/46 ,  H04L27/00

CPC分类号： H04L5/1446 ,  H04L1/0002 ,  H04L1/0025

摘要： An interface for use in a local device includes a transmitter portion programmably configurable to at least three data rates, a receiver portion programmably configurable to those at least three data rates, and an automatic speed negotiation module operatively connected to the transmitter portion and the receiver portion to configure the transmitter portion and the receiver portion for communication with a remote device at a single data rate that is a best available one of those at least three data rates. The date rate can be adjusted by adjusting transmitter data path width and receiver data path width, adjusting a frequency of said transmitter data path and said receiver data path, and oversampling. Byte serialization or deserialization can be enabled or disabled to alter the width of the data, depending on the data rate, for transfer to/from the remainder of the local device.

摘要翻译： 用于本地设备的接口包括可编程地配置为至少三个数据速率的发射机部分，可编程地配置为至少三个数据速率的接收机部分，以及可操作地连接到发射机部分和接收机部分的自动速度协商模块 配置发射机部分和接收机部分，以与作为这些至少三个数据速率中最好的可用数据速率的单个数据速率与远程设备进行通信。 可以通过调整发射机数据路径宽度和接收机数据路径宽度，调整所述发射机数据路径和所述接收机数据路径的频率以及过采样来调整日期速率。 可以使能或禁用字节序列化或反序列化，以根据数据速率改变数据的宽度，以传输到/从本地设备的其余部分。

公开(公告)号：US08291255B1

公开(公告)日：2012-10-16

申请号：US13082162

申请日：2011-04-07

申请人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Lana May Chan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Lana May Chan ,  Chong H. Lee

IPC分类号： G06F1/00 ,  H04L7/00 ,  H04L7/02

CPC分类号： G06F13/4295 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/10 ,  Y02D10/14 ,  Y02D10/151

摘要： Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface, between its “lock-to-reference” (“LTR”) state and its normal “lock-to-data” (“LTD”) state. Whenever during this toggling mode the CDR circuitry toggles to the LTD state, it remains in that state for a predetermined interval and then returns to the LTR state, unless, while it is in the LTD state, it receives a signal from elsewhere in the receiver that data have been received and byte synchronization has occurred. The predetermined toggling interval preferably is long enough to obtain an LTR lock to minimize frequency drift, but short enough to avoid unnecessary delay in detection of the synchronization signal. Preferably, this interval is programmable by the user within limits determined by the characterization of the programmable device. Unreliable analog signal detection is thereby avoided.

摘要翻译： 可编程集成电路设备上的高速串行接口的时钟数据恢复（CDR）电路在接口的接收机的电气空闲周期内切换其锁定参考（LTR）状态与其正常的锁定 - 数据（LTD）状态。 无论何时在这个切换模式下，CDR电路切换到LTD状态，它保持在该状态一段预定的间隔，然后返回到LTR状态，除非在它处于LTD状态时，它接收来自接收器中其他地方的信号 已经接收到数据并发生字节同步。 预定的切换间隔优选地足够长以获得LTR锁定以使频率漂移最小化，但足够短以避免对同步信号的检测的不必要的延迟。 优选地，该间隔可由用户在由可编程设备的表征确定的限度内编程。 从而避免了不可靠的模拟信号检测。

公开(公告)号：US07684477B1

公开(公告)日：2010-03-23

申请号：US11490406

申请日：2006-07-19

申请人： Divya Vijayaraghavan ,  Chong H. Lee

发明人： Divya Vijayaraghavan ,  Chong H. Lee

IPC分类号： H04B3/46

CPC分类号： H04L1/0002

摘要： A serial interface for a programmable logic device includes receiver and transmitter portions, and an automatic speed negotiation module to adjust the data rates of both portions. The speed adjustment may be accomplished by adjusting the widths of the data paths in both portions. The speed adjustment occurs on receipt of a control signal generated elsewhere on the programmable logic device, or generated by the module. One reason for generating the control signal is the detection of data errors in the received data, or the detection of a delimiter pattern in the received data signifying that a remote device is about to change its data rate.Similarly, before changing its data rate, the module may insert a delimiter in the data in the transmitter portion. After receipt or transmission of a delimiter pattern, the module may wait for a predetermined delay period to elapse before changing the data rate.

摘要翻译： 用于可编程逻辑器件的串行接口包括接收器和发送器部分，以及用于调整两部分的数据速率的自动速度协商模块。 速度调整可以通过调整两部分中数据路径的宽度来实现。 速度调整发生在接收到可编程逻辑器件其他地方生成的或由模块生成的控制信号。 产生控制信号的一个原因是检测接收到的数据中的数据错误，或者检测到接收到的数据中的定界符模式，这意味着远程设备即将改变其数据速率。 类似地，在改变其数据速率之前，模块可以在发射机部分的数据中插入定界符。 在接收或发送分隔符模式之后，模块可以在改变数据速率之前等待预定的延迟时间段。

公开(公告)号：US07627806B1

公开(公告)日：2009-12-01

申请号：US11436463

申请日：2006-05-17

申请人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Chong H. Lee ,  Ning Xue ,  Tam Nguyen

发明人： Divya Vijayaraghavan ,  Michael Menghui Zheng ,  Chong H. Lee ,  Ning Xue ,  Tam Nguyen

IPC分类号： H03M13/09

CPC分类号： H04L1/0052 ,  H03M13/09 ,  H03M13/6516 ,  H04L1/0061

摘要： A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).

摘要翻译： 可编程逻辑集成电路器件（“PLD”）包括至少部分硬接线以执行HSSI操作的至少一些功能方面的高速串行接口（“HSSI”）电路。 循环冗余校验（CRC）生成和/或检查电路现在包括在该HSSI电路中，并且再次，该CRC电路至少部分地硬接线以执行其操作的至少一些功能方面。

公开(公告)号：US20050083942A1

公开(公告)日：2005-04-21

申请号：US10671353

申请日：2003-09-25

申请人： Divya Vijayaraghavan ,  Curtis Ridgeway

发明人： Divya Vijayaraghavan ,  Curtis Ridgeway

IPC分类号： G06F15/173 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04L47/2441 ,  H04L47/2475 ,  H04L47/50 ,  H04L47/527 ,  H04L47/6235

摘要： A method and system prioritizes frames to be transmitted from a local node to a remote node on a Fibre Channel Arbitration Loop. The frames are placed in context queues. Each kind of context queue is assigned a priority. A determination of a set of transmit frame types is made. A user, an external device, or code may determine the number of transmit frame types in the set. A priority is assigned for each of the transmit frame types in the set. The transmit frame types may be determined by context type. The frames are prepared for transmission. The queues are examined by a suitable method to determine order of transmission. The transmit prioritizer preferably comprises five three-entry deep queues in which the prioritizer places valid contexts classified by transmit frame type. Queued contexts are selected for outgoing frame transmission by a prioritization algorithm aimed at saving the current fibre channel loop tenancy to maximize performance whenever possible. The context manager controls context storage and retrieval and the transmit prioritizer selects the context for which frame transfers will be performed.

摘要翻译： 一种方法和系统对要在光纤通道仲裁环路上从本地节点发送到远程节点的帧进行优先级排序。 帧被放置在上下文队列中。 每种上下文队列被分配优先级。 做出一组发送帧类型的确定。 用户，外部设备或代码可以确定集合中的发送帧类型的数量。 为集合中的每个发送帧类型分配优先级。 发送帧类型可以由上下文类型确定。 帧准备传输。 通过合适的方法检查队列以确定传输顺序。 发送优先级优先级优选地包括五个三进入深队列，其中优先级排序器放置通过发送帧类型分类的有效上下文。 通过优先级算法选择排队上下文，用于节省当前光纤通道循环租约，以尽可能地最大限度地提高性能。 上下文管理器控制上下文存储和检索，并且发送优先级选择器将选择将执行哪些帧传送的上下文。

公开(公告)号：US07573870B2

公开(公告)日：2009-08-11

申请号：US10671353

申请日：2003-09-25

申请人： Divya Vijayaraghavan ,  Curtis Ridgeway

发明人： Divya Vijayaraghavan ,  Curtis Ridgeway

IPC分类号： H04L12/28

CPC分类号： H04L47/2441 ,  H04L47/2475 ,  H04L47/50 ,  H04L47/527 ,  H04L47/6235

摘要： A method and system prioritizes frames to be transmitted from a local node to a remote node on a Fibre Channel Arbitration Loop. The frames are placed in context queues. Each kind of context queue is assigned a priority. A determination of a set of transmit frame types is made. A user, an external device, or code may determine the number of transmit frame types in the set. A priority is assigned for each of the transmit frame types in the set. The transmit frame types may be determined by context type. The frames are prepared for transmission. The queues are examined by a suitable method to determine order of transmission. The transmit prioritizer preferably comprises five three-entry deep queues in which the prioritizer places valid contexts classified by transmit frame type. Queued contexts are selected for outgoing frame transmission by a prioritization algorithm aimed at saving the current fibre channel loop tenancy to maximize performance whenever possible. The context manager controls context storage and retrieval and the transmit prioritizer selects the context for which frame transfers will be performed.

摘要翻译： 一种方法和系统对要在光纤通道仲裁环路上从本地节点发送到远程节点的帧进行优先级排序。 帧被放置在上下文队列中。 每种上下文队列被分配优先级。 做出一组发送帧类型的确定。 用户，外部设备或代码可以确定集合中的发送帧类型的数量。 为集合中的每个发送帧类型分配优先级。 发送帧类型可以由上下文类型确定。 帧准备传输。 通过合适的方法检查队列以确定传输顺序。 发送优先级优先级优选地包括五个三进入深队列，其中优先级排序器放置通过发送帧类型分类的有效上下文。 通过优先级算法选择排队上下文，用于节省当前光纤通道循环租约，以尽可能地最大限度地提高性能。 上下文管理器控制上下文存储和检索，并且发送优先级选择器将选择将执行哪些帧传送的上下文。