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公开(公告)号：US06928525B1
公开(公告)日：2005-08-09
申请号：US09560907
申请日：2000-04-28
申请人： Sharon M. Ebner , John A. Wickeraad
发明人： Sharon M. Ebner , John A. Wickeraad
CPC分类号： G06F12/0857 , G06F12/084
摘要： A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whether that particular cache line is in use, and is used to arbitrate among various requesters for the same cache line. When at least two requests for the same cache line is received, a cache arbiter examines the status bit to determine if the requested cache line is in use. If the cache line is not already in use, the cache arbiter selects, and sends a signal granting the request to, the requesters one at a time to allow access to the contested cache line, while allowing concurrent access to the cache memory to other requesters requesting different cache lines. The semaphore mechanism allows exchanges of signals between the cache arbiter and the requesters to provide an orderly arbitration of multiple requests for the same cache line.
摘要翻译： 多端口缓存存储器系统中的信号量机制允许并发访问高速缓冲存储器。 当同一缓存行没有争用时，多个请求者可以同时访问高速缓存。 每个高速缓存行中的状态位指示该特定高速缓存行是否在使用中，并且用于在相同高速缓存行的不同请求者之间进行仲裁。 当接收至少两个相同高速缓存行的请求时，缓存仲裁器检查状态位以确定所请求的高速缓存行是否正在使用。 如果高速缓存行尚未使用，则高速缓存仲裁器一次选择一个授权请求的请求者，以允许访问有争议的高速缓存行，同时允许对其他请求者的高速缓冲存储器的并发访问 请求不同的缓存行。 信号量机制允许高速缓存仲裁器和请求者之间的信号交换，以提供对相同高速缓存行的多个请求的有序仲裁。
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12.发明授权公开(公告)号：US06647469B1
公开(公告)日：2003-11-11
申请号：US09562191
申请日：2000-05-01
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In the coherent mode, the memory controller ensures that the data stored in system memory is accurately and precisely mirrored in all subservient copies of that data as might typically be stored in agent cache memories. Using, for example, a MESI type protocol, the memory controller limits access to memory so that only an “owner” or a particular portion or line of memory has write access and that, during the extension of these write privileges, no other agent has a valid copy of the data subject to being updated. Thus, the memory controller implements a first set of rule in the coherent mode of operation to insure that all copies of data stored by the agents are coherent with data stored in the memory. In a read current mode of access, a read-once segment of data is copied to an agent with the agent implementing a second set of rules to minimize or eliminate the possibility that the data might become stale prior to use or that it be misused by another agent or process. Thus, in the read current, an “uncontrolled” copy of the data is released subject to certain restrictions to be implemented by the receiving agent as defined by a second set of rules. For example, these rules require that the agent's copy of data be provided as an output and then invalidated within a predetermined period of time, that the agent have limit access to the memory during any set of fetch operations to no more than a predetermined maximum block size. Also included is a requirement that the copy of data include only that data contained within a range of memory addresses, the range beginning within a predetermined block of memory addresses and continuing through an end of block address. These limitations limit the amount of data that might be subject to misuse, particularly in the case of a failure resulting in the inability of a requesting agent to complete a transaction according to the rules.
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公开(公告)号：US08046642B2
公开(公告)日：2011-10-25
申请号：US12569397
申请日：2009-09-29
CPC分类号： G11C29/816 , G11C15/00 , G11C29/44 , G11C29/76
摘要： A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.
摘要翻译： 一种在三元内容可寻址存储器（TCAM）中提供冗余的方法，所述方法包括检测三元内容可寻址存储器（TCAM）中的构建块中的缺陷条目，配置故障转移逻辑以将软件查询重定向到备用构建块，以及 远离具有缺陷进入的构件块，并且避免使用具有缺陷入口的构造块。
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公开(公告)号：US07596741B2
公开(公告)日：2009-09-29
申请号：US11102973
申请日：2005-04-11
IPC分类号： H03M13/00
CPC分类号： H04L1/0045 , H04L1/0061 , H04L1/0072 , H04L2001/0098
摘要： A network device is provided which can include logic associated with the operations of a data communications protocol stack. The logic can operate to receive a packet to the network device and apply a first error checking technique, having a first modification complexity, to a header of the packet. The logic can apply a second error checking technique, having a second modification complexity that is greater than the first modification complexity, to a body of the packet. A first verification key can be provided to a first header associated with the packet and a second verification key, having a different modification complexity from the first verification key, can be provided for a second header associated with the packet.
摘要翻译： 提供了一种网络设备，其可以包括与数据通信协议栈的操作相关联的逻辑。 逻辑可以操作以向网络设备接收分组，并将具有第一修改复杂度的第一错误检查技术应用于分组的报头。 该逻辑可以向分组的主体应用具有大于第一修改复杂度的第二修改复杂度的第二错误检查技术。 可以向与分组相关联的第一报头提供第一验证密钥，并且可以为与分组相关联的第二报头提供具有来自第一验证密钥的不同修改复杂度的第二验证密钥。
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公开(公告)号：US20080301362A1
公开(公告)日：2008-12-04
申请号：US11810072
申请日：2007-06-04
摘要： Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison.
摘要翻译： 提供系统，设备和方法，包括可执行指令，用于解析内容可寻址存储器（CAM）匹配地址优先级。 一种方法包括保留第一匹配地址作为最佳匹配地址。 将后续匹配地址与保留的最佳匹配地址进行比较，每个匹配地址与比较周期相关联，在该比较周期期间，将每个CAM条目的选定柱状部分与搜索项的相应部分进行比较。 作为比较的结果，最佳匹配地址被更新。
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公开(公告)号：US20080259667A1
公开(公告)日：2008-10-23
申请号：US11787588
申请日：2007-04-17
申请人： John A. Wickeraad
发明人： John A. Wickeraad
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content addressable memory (TCAM). The method includes marking certain entries as valid. The method includes precharging match lines associated with the entries when an entry is valid and based on a type selection.
摘要翻译： 为内容可寻址存储器（CAM）提供系统，设备和方法，包括可执行指令。 一种方法包括将包括类型字段的条目写入三进制内容可寻址存储器（TCAM）。 该方法包括将某些条目标记为有效。 该方法包括当条目有效并且基于类型选择时预充电与条目相关联的匹配行。
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17.发明授权公开(公告)号：US06636906B1
公开(公告)日：2003-10-21
申请号：US09560553
申请日：2000-04-28
IPC分类号： G06F1328
CPC分类号： G06F12/0835
摘要： A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein disclosed. Attributes that uniquely identify the original I/O device and DMA read request are stored in a cache tag unit. A read lock is set when a request is made to obtain the requested data when it is not resident in a local cache. When the cache line containing the requested data is snooped out and the read lock is set, then the cache line is set in a snapshot state. The snapshot state assures that only the original I/O device receives the read data when it has been altered subsequent to the time the original DMA read request was made. Once the data is returned to the original I/O device, the cache line is invalidated in order to prevent another I/O device from reading the stale data. Prefetched data is marked as such and cannot be marked as snapshot data.
摘要翻译： 本文公开了一种快照机制，其包括用于跟踪在将数据返回到请求的I / O设备之前可以改变的可缓存数据的DMA读取请求的装置和方法。 唯一标识原始I / O设备和DMA读取请求的属性存储在缓存标签单元中。 当请求的数据不驻留在本地缓存中时，请求获取请求的数据时，设置读锁定。 当包含请求的数据的高速缓存行被窥探并设置了读锁定时，缓存行被设置为快照状态。 快照状态确保只有原始I / O设备在原始DMA读取请求的时间之后被更改时才接收读取的数据。 一旦将数据返回到原始I / O设备，高速缓存行将无效，以防止其他I / O设备读取陈旧的数据。 预取数据被标记为不能被标记为快照数据。
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18.发明授权公开(公告)号：US06587893B1
公开(公告)日：2003-07-01
申请号：US09560168
申请日：2000-04-28
申请人： John A. Wickeraad
发明人： John A. Wickeraad
IPC分类号： G06F1314
CPC分类号： G06F13/122
摘要： A method and apparatus determines completion of all of one or more operations for a particular input/output device initiated prior to an inquiry start time. The method provides one or more in-progress bits and an equal number of snapshot bits. Each in-progress bit corresponds to a respective associated operation for the input/output device. An in-progress bit is set when the associated operation is initiated. The in-progress bit is cleared when the associated operation is completed. The method copies, at the inquiry start time, all of the in-progress bits to the corresponding snapshot bits and clears a snapshot bit when the associated operations is completed. Finally, the method determines whether every one of said one or more snapshot bits is cleared. The apparatus comprises an input/output operator, one or more operation requesters, one or more in-progress bits and an equal number of snapshot bits. Preferably, the in-progress bits are grouped in a register, as are the snapshot bits. Each in-progress bit corresponds to a respective associated operation for the input/output devices, is set when the associated operation is initiated, and is cleared when the associated operations is completed.
摘要翻译： 方法和装置确定在查询开始时间之前启动的特定输入/输出设备的一个或多个操作的全部完成。 该方法提供一个或多个进行中的比特和相等数量的快照比特。 每个进行中的位对应于输入/输出设备的相应的相关操作。 当相关操作启动时，进行中的位置位。 当相关操作完成时，进行中的位被清除。 该方法在查询开始时将所有正在进行的比特复制到相应的快照比特，并在关联的操作完成时清除快照位。 最后，该方法确定所述一个或多个快照位中的每一个是否被清除。 该装置包括输入/输出运算符，一个或多个操作请求者，一个或多个进行中的比特和相等数量的快照比特。 优选地，正在进行的比特被分组在寄存器中，以及快照比特。 每个进行中的位对应于对于输入/输出设备的相应的相关联的操作，在相关联的操作被启动时被设置，并且当相关联的操作完成时被清除。
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公开(公告)号：US07602629B2
公开(公告)日：2009-10-13
申请号：US11787588
申请日：2007-04-17
申请人： John A. Wickeraad
发明人： John A. Wickeraad
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Systems, devices, and methods, including executable instructions are provided for content addressable memory (CAM). One method includes writing entries, including a type field, to a ternary content addressable memory (TCAM). The method includes marking certain entries as valid. The method includes precharging match lines associated with the entries when an entry is valid and based on a type selection.
摘要翻译： 为内容可寻址存储器（CAM）提供系统，设备和方法，包括可执行指令。 一种方法包括将包括类型字段的条目写入三进制内容可寻址存储器（TCAM）。 该方法包括将某些条目标记为有效。 该方法包括当条目有效并且基于类型选择时预充电与条目相关联的匹配行。
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公开(公告)号：US07480590B2
公开(公告)日：2009-01-20
申请号：US10863256
申请日：2004-06-09
CPC分类号： G06F11/348 , G06F2201/88
摘要： A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can also trigger the performance adder through atomic, edge, toggle, or on/off signals related to the performance events or through a logical function of a combination of performance events. The performance adders can be used to compute average latency of a component in the circuit.
摘要翻译： 一种性能加法器，用于在集成电路芯片内提供运行中的性能值总计。 性能加法器由通过多路复用器逻辑确定的各种性能事件触发，用于检测特定性能事件的发生。 复用器逻辑还可以通过与性能事件相关的原子，边沿，触发或开启/关闭信号或通过性能事件的组合的逻辑功能来触发性能加法器。 性能加法器可用于计算电路中组件的平均延迟。
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