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1.发明授权公开(公告)号：US06647469B1
公开(公告)日：2003-11-11
申请号：US09562191
申请日：2000-05-01
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/621
摘要： A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In the coherent mode, the memory controller ensures that the data stored in system memory is accurately and precisely mirrored in all subservient copies of that data as might typically be stored in agent cache memories. Using, for example, a MESI type protocol, the memory controller limits access to memory so that only an “owner” or a particular portion or line of memory has write access and that, during the extension of these write privileges, no other agent has a valid copy of the data subject to being updated. Thus, the memory controller implements a first set of rule in the coherent mode of operation to insure that all copies of data stored by the agents are coherent with data stored in the memory. In a read current mode of access, a read-once segment of data is copied to an agent with the agent implementing a second set of rules to minimize or eliminate the possibility that the data might become stale prior to use or that it be misused by another agent or process. Thus, in the read current, an “uncontrolled” copy of the data is released subject to certain restrictions to be implemented by the receiving agent as defined by a second set of rules. For example, these rules require that the agent's copy of data be provided as an output and then invalidated within a predetermined period of time, that the agent have limit access to the memory during any set of fetch operations to no more than a predetermined maximum block size. Also included is a requirement that the copy of data include only that data contained within a range of memory addresses, the range beginning within a predetermined block of memory addresses and continuing through an end of block address. These limitations limit the amount of data that might be subject to misuse, particularly in the case of a failure resulting in the inability of a requesting agent to complete a transaction according to the rules.
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2.发明授权公开(公告)号：US06636906B1
公开(公告)日：2003-10-21
申请号：US09560553
申请日：2000-04-28
IPC分类号： G06F1328
CPC分类号： G06F12/0835
摘要： A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein disclosed. Attributes that uniquely identify the original I/O device and DMA read request are stored in a cache tag unit. A read lock is set when a request is made to obtain the requested data when it is not resident in a local cache. When the cache line containing the requested data is snooped out and the read lock is set, then the cache line is set in a snapshot state. The snapshot state assures that only the original I/O device receives the read data when it has been altered subsequent to the time the original DMA read request was made. Once the data is returned to the original I/O device, the cache line is invalidated in order to prevent another I/O device from reading the stale data. Prefetched data is marked as such and cannot be marked as snapshot data.
摘要翻译： 本文公开了一种快照机制，其包括用于跟踪在将数据返回到请求的I / O设备之前可以改变的可缓存数据的DMA读取请求的装置和方法。 唯一标识原始I / O设备和DMA读取请求的属性存储在缓存标签单元中。 当请求的数据不驻留在本地缓存中时，请求获取请求的数据时，设置读锁定。 当包含请求的数据的高速缓存行被窥探并设置了读锁定时，缓存行被设置为快照状态。 快照状态确保只有原始I / O设备在原始DMA读取请求的时间之后被更改时才接收读取的数据。 一旦将数据返回到原始I / O设备，高速缓存行将无效，以防止其他I / O设备读取陈旧的数据。 预取数据被标记为不能被标记为快照数据。
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3.发明授权Method and apparatus for using the unused bits of a data packet to transmit additional information 失效用于使用数据分组的未使用位来发送附加信息的方法和装置
公开(公告)号：US5944843A
公开(公告)日：1999-08-31
申请号：US918696
申请日：1997-08-21
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0083 , H04L1/1671 , H04L47/35 , H04L1/16 , H04L2001/0095 , H04L69/22 , H04L69/324
摘要： A method and apparatus in accordance with the present invention uses the unused bits of a data packet to transmit additional information by piggy-backing "secondary" code words into a data packet containing a "primary" code word. A secondary code word may be piggy-backed into a data packet containing a primary code word when the primary code word and any secondary code words already stored in the data packet leave sufficient unused space in the data packet to store an additional secondary code word, and the route traveled by the data packet as the packet is routed to the network node addressed by the primary code passes through (or ends at) the network node addressed by the secondary code word, or passes through (or ends at) a network node that can relay the secondary code word to the network node addressed by the secondary code word. In a first embodiment, an ECC is generated for the primary code word using a predefined bit pattern (such as all 0's) for any unused bit positions in the data packet. The same predefined bit pattern is used for the unused bit positions when the integrity of the primary code word is verified at the destination. If it is desired to protect the secondary code word, a secondary ECC must also be stored in the data packet. In a second embodiment, the ECC is recalculated when a secondary code word is piggy-backed into the unused bit positions of the data packet. In this embodiment, the ECC associated with the data packet protects all data in the packet, including the primary and secondary code words.
摘要翻译： 根据本发明的方法和装置使用数据分组的未使用的比特通过捎带“次”码字来发送附加信息到包含“主”码字的数据分组中。 当主代码字和已经存储在数据分组中的任何辅助代码字在数据分组中留下足够的未使用空间以存储额外的辅助代码字时，副代码字可以被捎带到包含主代码字的数据分组中， 并且当分组被路由到由主代码寻址的网络节点时由数据分组传播的路由通过（或在其结束于）由第二代码字寻址的网络节点，或者通过（或最终）网络节点 可以将次要码字中继到由二次码字寻址的网络节点。 在第一实施例中，为数据分组中的任何未使用位位置使用预定义位模式（例如全0）为主代码字生成ECC。 当在目的地验证主码字的完整性时，相同的预定位位模式用于未使用的位位置。 如果希望保护辅助码字，则辅助ECC也必须存储在数据包中。 在第二实施例中，当第二码字被捎带到数据包的未使用位位置时，重新计算ECC。 在该实施例中，与数据分组相关联的ECC保护分组中的所有数据，包括主要和次要代码字。
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4.发明授权公开(公告)号：US06631428B1
公开(公告)日：2003-10-07
申请号：US09562489
申请日：2000-05-01
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.
摘要翻译： 这里提供了一种机制，其包括用于确保任何流控制类中的所有事务完成的装置和方法。 该机制包括插入到每个挂起的事务队列中的插入事务，并将其发送到特定目的地设备。 当目标设备在流控制类中接收到插入事务时，流控制类中的所有先前事务被认为是完整的。
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公开(公告)号：US07325164B2
公开(公告)日：2008-01-29
申请号：US10670620
申请日：2003-09-25
IPC分类号： G06F11/00
CPC分类号： G01R31/318522
摘要： Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.
摘要翻译： 测试电路与要测试的电路（例如ASIC或微处理器）一起并入芯片管芯，以提供对集成电路芯片封装内部的信号的外部访问。 控制器提供arm命令并发出适当的配置控制来收集信号样本。 特别地，网络响应来自控制器的这些命令，以选择性地提供来自被测器件的信号样本。 触发事件发生器响应信号样本的逻辑或其他特性以提供触发事件。 这些触发事件由处于状态机的布防状态的触发事件计数器进行计数，以识别对应于触发事件的可编程数量的发生的最终触发事件。 存储事件发生器还响应编程的特征或信号样本的组合以提供存储事件。 事件发生器中的一个或两个可以使用掩码来提供这些事件。
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公开(公告)号：US06928525B1
公开(公告)日：2005-08-09
申请号：US09560907
申请日：2000-04-28
申请人： Sharon M. Ebner , John A. Wickeraad
发明人： Sharon M. Ebner , John A. Wickeraad
CPC分类号： G06F12/0857 , G06F12/084
摘要： A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whether that particular cache line is in use, and is used to arbitrate among various requesters for the same cache line. When at least two requests for the same cache line is received, a cache arbiter examines the status bit to determine if the requested cache line is in use. If the cache line is not already in use, the cache arbiter selects, and sends a signal granting the request to, the requesters one at a time to allow access to the contested cache line, while allowing concurrent access to the cache memory to other requesters requesting different cache lines. The semaphore mechanism allows exchanges of signals between the cache arbiter and the requesters to provide an orderly arbitration of multiple requests for the same cache line.
摘要翻译： 多端口缓存存储器系统中的信号量机制允许并发访问高速缓冲存储器。 当同一缓存行没有争用时，多个请求者可以同时访问高速缓存。 每个高速缓存行中的状态位指示该特定高速缓存行是否在使用中，并且用于在相同高速缓存行的不同请求者之间进行仲裁。 当接收至少两个相同高速缓存行的请求时，缓存仲裁器检查状态位以确定所请求的高速缓存行是否正在使用。 如果高速缓存行尚未使用，则高速缓存仲裁器一次选择一个授权请求的请求者，以允许访问有争议的高速缓存行，同时允许对其他请求者的高速缓冲存储器的并发访问 请求不同的缓存行。 信号量机制允许高速缓存仲裁器和请求者之间的信号交换，以提供对相同高速缓存行的多个请求的有序仲裁。
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公开(公告)号：US06662313B1
公开(公告)日：2003-12-09
申请号：US09563059
申请日：2000-04-29
IPC分类号： G06F1100
CPC分类号： G01R31/318522
摘要： Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioning from a standby state to an armed state, (ii) a final trigger event for transitioning from the armed state to a triggered state, and (iii) a post trigger count event for transitioning from the triggered state to the standby state. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events. A post trigger sample counter operates in the triggered state to provide the post trigger count event in response to a programmable number of signal samples being captured. A memory operates in the triggered state to store the samples being captured. The memory may optionally store samples in the armed state which occur prior to the targeted samples so as to provide test data from cycles prior to the targeted events.
摘要翻译： 测试电路与要测试的电路（例如ASIC或微处理器）一起并入芯片管芯，以提供对集成电路芯片封装内部的信号的外部访问。 测试装置包括响应于（i）从待机状态转移到武装状态的臂命令的状态机，（ii）从武装状态转换到触发状态的最终触发事件，以及（iii） 触发计数事件从触发状态转换到待机状态。 控制器提供arm命令并发出适当的配置控制来收集信号样本。 特别地，网络响应来自控制器的这些命令，以选择性地提供来自被测器件的信号样本。 触发事件发生器响应信号样本的逻辑或其他特性以提供触发事件。 这些触发事件由处于状态机的布防状态的触发事件计数器进行计数，以识别对应于触发事件的可编程数量的发生的最终触发事件。 存储事件发生器还响应编程的特征或信号样本的组合以提供存储事件。 事件发生器中的一个或两个可以使用掩码来提供这些事件。 后触发采样计数器在触发状态下操作以响应于可捕获的可编程数量的信号样本来提供后触发计数事件。 存储器在触发状态下操作以存储被捕获的样本。 存储器可以可选地存储在目标样本之前发生的布防状态的样本，以便在目标事件之前的周期提供测试数据。
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8.发明授权Systems and methods for prefetch operations to reduce latency associated with memory access 失效用于预取操作的系统和方法，以减少与内存访问相关的延迟公开(公告)号：US06718454B1
公开(公告)日：2004-04-06
申请号：US09563060
申请日：2000-04-29
申请人： Sharon M. Ebner , John A. Wickeraad
发明人： Sharon M. Ebner , John A. Wickeraad
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F12/0862 , G06F13/161 , G06F2212/6022
摘要： A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval of data stored at the requested address, while a prefetch machine predicts future requests and keeps track of memory requests already initiated and queued. Thus, the prefetch machine is responsive to the plurality addresses to predict others of the addresses and provide or initiate retrieval of data stored thereat. To avoid prefetching information already requested and in a fetch queue, the prefetch machine includes a memory storing a last one of the addresses subject to prefetching. Finally, to avoid conflicts between currently requested data and prefetch operation, an arbiter resolves memory accesses or data requests initiated by the fetch and prefetch machines.
摘要翻译： 数据处理系统包括存储要被检索的数据的存储器和被配置为以多个地址请求存储在存储器中的数据的I / O控制器。 I / O可以响应于请求这样的数据的内部或外部设备。 提取机器提供或启动对在请求的地址处存储的数据的检索，而预取机器预测未来请求并且跟踪已经发起和排队的存储器请求。 因此，预取机器响应于多个地址来预测其他地址，并提供或启动对其上存储的数据的检索。 为了避免预取已经请求的信息并且在获取队列中，预取机器包括存储存储预取的最后一个地址的存储器。 最后，为了避免当前请求的数据和预取操作之间的冲突，仲裁器解决由获取和预取机器发起的内存访问或数据请求。
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公开(公告)号：US07760530B2
公开(公告)日：2010-07-20
申请号：US11810072
申请日：2007-06-04
IPC分类号： G11C15/00
摘要： Systems, devices, and methods, including executable instructions are provided for resolving content addressable memory (CAM) match address priority. One method includes retaining a first match address as the best match address. Subsequent match addresses are compared to the retained best match address, each match address being associated with a compare cycle during which a selected columnar portion of each CAM entry is compared to a corresponding portion of a search term. The best match address is updated as a result of the comparison.
摘要翻译： 提供系统，设备和方法，包括可执行指令，用于解析内容可寻址存储器（CAM）匹配地址优先级。 一种方法包括保留第一匹配地址作为最佳匹配地址。 将后续匹配地址与保留的最佳匹配地址进行比较，每个匹配地址与比较周期相关联，在该比较周期期间，将每个CAM条目的选定柱状部分与搜索项的相应部分进行比较。 作为比较的结果，最佳匹配地址被更新。
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公开(公告)号：US20100023804A1
公开(公告)日：2010-01-28
申请号：US12569397
申请日：2009-09-29
IPC分类号： G06F11/20
CPC分类号： G11C29/816 , G11C15/00 , G11C29/44 , G11C29/76
摘要： A method of providing redundancy in a ternary content addressable memory (TCAM), the method including detecting a defective entry in building block in a ternary content addressable memory (TCAM), configuring a failover logic to redirect a software query toward a spare building block and away from the building block with the defective entry, and avoiding in using the building block with the defective entry.
摘要翻译： 一种在三元内容可寻址存储器（TCAM）中提供冗余的方法，所述方法包括检测三元内容可寻址存储器（TCAM）中的构建块中的缺陷条目，配置故障转移逻辑以将软件查询重定向到备用构建块，以及 远离具有缺陷进入的构件块，并且避免使用具有缺陷入口的构造块。
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