公开(公告)号：US4247936A

公开(公告)日：1981-01-27

申请号：US45860

申请日：1979-06-06

申请人： Charles H. Hustig

发明人： Charles H. Hustig

IPC分类号： H04J3/06

CPC分类号： H04J3/0602

摘要： Digital communication system of the type having a commutating N:1 multiplexer and a commutating 1:N demultiplexer. One of the N sources is inverted prior to being applied to the multiplexer. Automatic frame synchronization and detection circuitry is provided which repeatedly monitors the output of the demultiplexer at which the inverted signal is to appear when frame synchronization is present. Such output is monitored for signals of one logic during each monitoring time period to determine whether frame synchronization is present. A signal is obtained by such circuitry when frame synchronization is not present and is used to commutate the demultiplexer a predetermined number of steps whereby frame synchronization is attained.

摘要翻译： 具有换向N：1多路复用器和换向1：N解复用器的类型的数字通信系统。 其中一个N源在施加到多路复用器之前被反相。 提供了自动帧同步和检测电路，其重复地监视当存在帧同步时将出现反相信号的解复用器的输出。 在每个监视时间周期期间监视这样一个逻辑的信号，以确定是否存在帧同步。 当不存在帧同步时，通过这种电路获得信号，并且用于将解复用器换向预定数量的步骤，由此获得帧同步。

公开(公告)号：US4264973A

公开(公告)日：1981-04-28

申请号：US968843

申请日：1978-12-13

申请人： Charles H. Hustig

发明人： Charles H. Hustig

IPC分类号： H04L7/027 ,  H04L25/49 ,  H04L7/06

CPC分类号： H04L7/0008 ,  H04L25/4904 ,  H04L7/027

摘要： Circuitry is disclosed for transmitting clock signal information with a transmitted signal. The transmitted signal is obtained by applying non-return to zero input pulse signals, provided at one-half the frequency of the clock signal, with alternate "1" logic and "0" logic signals, which are coincident with the transitions in the pulse signals, to an exclusive-or logic circuit and combining the output of the exclusive-or logic circuit with the alternate "1" and "0" logic signals at an adder circuit. The adder circuit provides an output that is a succession of signals at one-half the frequency of the clock signal with each of the successive signals having an amplitude different than the amplitude of the preceding signal. The logic signals provided to the adder circuit have an amplitude equal to or greater than the output of the exclusive-or logic circuit. Circuitry is also disclosed for recovering the clock information from the signal provided from the adder and for reconstructing the input pulse signals.

摘要翻译： 公开了用于发送具有发送信号的时钟信号信息的电路。 发送信号通过将不返回到以时钟信号的一半频率提供的零输入脉冲信号与与脉冲中的转变一致的可选的“1”逻辑和“0”逻辑信号 信号发送到异或逻辑电路，并将异或逻辑电路的输出与加法器电路中的交替“1”和“0”逻辑信号组合。 加法器电路提供输出，该输出是时钟信号频率的一半的一系列信号，其中每个连续信号的幅度不同于先前信号的振幅。 提供给加法器电路的逻辑信号的幅度等于或大于异或逻辑电路的输出。 还公开了用于从加法器提供的信号中恢复时钟信息并重构输入脉冲信号的电路。