公开(公告)号：US20180124548A1

公开(公告)日：2018-05-03

申请号：US15720228

申请日：2017-09-29

Applicant: Konica Minolta, Inc.

Inventor： Kazuhiro Tomiyasu ,  Yoichi Kurumasa ,  Shoko Haba ,  Mie Kawabata ,  Ryosuke Nishimura ,  Zhenhuan Qu

IPC: H04W4/00 ,  H04W56/00 ,  H04L29/04 ,  H04L1/00 ,  H04J3/06

CPC classification number: H04W4/70 ,  H04J3/0602 ,  H04L1/0076 ,  H04L29/04 ,  H04L67/02 ,  H04L67/04 ,  H04L67/08 ,  H04L67/18 ,  H04W56/001

Abstract: An information processing device of a cooperative system that further includes a portable device includes: a display that displays an image; a position detector that detects a position on a display surface of the display with which an object has made contact; and a hardware processor that detects the portable device in response to the position detector detecting a position with which an object has made contact, establishes a communication path with the portable device, switches an independent mode not cooperating with the portable device to a cooperation mode cooperating with the portable device when a communication path with the portable device is established and the portable device is detected by the hardware processor, and displays a related image that is related to the portable device on the display in response to the hardware processor no longer detecting the portable device in the cooperation mode.

公开(公告)号：US09609609B2

公开(公告)日：2017-03-28

申请号：US14449512

申请日：2014-08-01

Applicant: ABB Technology AG

Inventor： Bernhard Deck ,  Thomas Küng

IPC: H04L12/06 ,  H04W56/00 ,  H04J3/16 ,  H04Q9/00 ,  H04J3/06

CPC classification number: H04W56/0015 ,  H04J3/0602 ,  H04J3/1688 ,  H04Q9/00

Abstract: Exemplary embodiments for updating a controller of a primary device of a power substation. An actual time is received from a time server via a cell phone communication network with a mobile device and the actual time is sent with the mobile device via a local wireless communication network to the controller.

公开(公告)号：US20160352388A1

公开(公告)日：2016-12-01

申请号：US14724487

申请日：2015-05-28

Applicant: QUALCOMM INCORPORATED

Inventor： Frank Lane

IPC: H04B3/54 ,  H04B1/3822 ,  H04W56/00 ,  H04L7/033

CPC classification number: H04B3/54 ,  G01S13/87 ,  G01S13/931 ,  G01S17/87 ,  G01S17/936 ,  G01S2013/9367 ,  H04B1/3822 ,  H04B2203/5408 ,  H04B2203/5445 ,  H04B2203/547 ,  H04J3/0602 ,  H04J3/0644 ,  H04J3/0655 ,  H04L7/0331 ,  H04L7/08 ,  H04L12/403 ,  H04W56/0015

Abstract: A network such as an in-vehicle powerline communication (PLC) network may allow PLC nodes to communicate over existing powerlines. Provided in the present disclosure are exemplary techniques for synchronizing network nodes (e.g., PLC nodes) with a network clock for the network so that data generated at each node may share a common time reference. For example, a synchronization (sync) signal may be generated by a master node and broadcast to other PLC nodes over a PLC channel, which may also carry data frames to and from other PLC nodes. The network clock may be autonomously generated by the master node or may be tied to an external clock.

Abstract translation: 诸如车载电力线通信（PLC）网络的网络可以允许PLC节点通过现有电力线进行通信。 在本公开中提供的是用于将网络节点（例如，PLC节点）与网络的网络时钟同步的示例性技术，使得在每个节点处生成的数据可以共享公共时间参考。 例如，同步（同步）信号可以由主节点产生并通过PLC信道广播到其他PLC节点，PLC信道也可以向其它PLC节点携带数据帧。 网络时钟可以由主节点自主生成或者可以被连接到外部时钟。

公开(公告)号：US09490962B2

公开(公告)日：2016-11-08

申请号：US14470804

申请日：2014-08-27

Applicant: Lattice Semiconductor Corporation

Inventor： Jiong Huang ,  Lei Ming ,  Gyudong Kim ,  Young Il Kim

IPC: H04L5/14 ,  H04J3/16 ,  H04J3/06 ,  G06F13/40 ,  H04L5/16

CPC classification number: H04L5/1415 ,  G06F13/40 ,  H04J3/0602 ,  H04J3/0617 ,  H04J3/16 ,  H04L5/1407 ,  H04L5/1469 ,  H04L5/16

Abstract: A multimedia system for data communications. A source device communicates over a full duplex control channel of a multimedia communication link using time domain multiplexed (TDM) frames having n time slots per frame. The source device allocates a first time slot position to a virtual channel for data transmission by the source device over the full duplex control channel. A sink device communicates over the full duplex control channel of the multimedia communication link. The sink device allocates a second time slot position to the virtual channel for data transmission by the sink device over the full duplex control channel. A timing of the second time slot position is offset from a timing of the first time slot position by substantially n/2 time slots.

Abstract translation: 一种用于数据通信的多媒体系统。 源设备使用具有每帧n个时隙的时域复用（TDM）帧在多媒体通信链路的全双工控制信道上进行通信。 源设备将虚拟信道的第一时隙位置分配给源设备通过全双工控制信道进行数据传输。 宿设备通过多媒体通信链路的全双工控制信道进行通信。 宿设备将虚拟信道的第二时隙位置分配给宿设备通过全双工控制信道进行数据传输。 第二时隙位置的定时偏离第一时隙位置的定时大致n / 2个时隙。

公开(公告)号：US09408169B2

公开(公告)日：2016-08-02

申请号：US14273028

申请日：2014-05-08

Applicant: AT&T Intellectual Property II, L.P.

Inventor： Saeed S. Ghassemzadeh ,  Robert Raymond Miller, II ,  John F. Murray

IPC: H04J3/06 ,  H04W56/00 ,  H04L7/00 ,  H04B1/7073 ,  H04B1/7075

CPC classification number: H04W56/001 ,  H04B1/7073 ,  H04B1/7075 ,  H04J3/0602 ,  H04J3/0611 ,  H04J3/0658 ,  H04L7/0008 ,  H04W84/12 ,  H04W88/08

Abstract: An arrangement for providing synchronization between a number of overlapping area access points within a wireless LAN utilizes an Ethernet cable connection to transmit synchronization signals from a centralized hub/switch to each of the access points connected to the cable. The synchronization signal takes the form of a direct sequence spread spectrum (DS-SS) signal.

Abstract translation: 用于在无线LAN内的多个重叠区域接入点之间提供同步的装置利用以太网电缆连接将同步信号从集中式集线器/交换机传送到连接到电缆的每个接入点。 同步信号采用直接序列扩频（DS-SS）信号的形式。

公开(公告)号：US09294263B2

公开(公告)日：2016-03-22

申请号：US14146654

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Mark Buckler ,  Wayne P. Burleson ,  Srilatha Manne

IPC: H04J3/06 ,  H04L7/02 ,  G06F1/12 ,  H04W56/00 ,  H04L7/033

CPC classification number: H04L7/02 ,  G06F1/12 ,  H04J3/0602 ,  H04J3/0632 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0331 ,  H04W56/001

Abstract: A circuit includes a plurality of synchronizers to adapt a signal from a first clock domain to a second clock domain. Each synchronizer of the plurality of synchronizers includes a synchronizer input to receive the signal from the first clock domain and a synchronizer output to provide the signal as adapted to the second clock domain. The circuit also includes a multiplexer (mux) that includes a plurality of mux inputs and a mux output. Each mux input is coupled to the synchronizer output of a respective synchronizer of the plurality of synchronizers. The mux output provides the signal, as adapted to the second clock domain, from the synchronizer output of a selected synchronizer of the plurality of synchronizers.

Abstract translation: 电路包括多个同步器，用于将来自第一时钟域的信号适配到第二时钟域。 多个同步器的每个同步器包括用于接收来自第一时钟域的信号的同步器输入和同步器输出以提供适合于第二时钟域的信号。 该电路还包括多路复用器（多路复用器），其包括多个多路复用器输入和多路复用器输出。 每个多路复用器输入耦合到多个同步器的相应同步器的同步器输出端。 多路复用器输出从多个同步器的所选同步器的同步器输出提供适应于第二时钟域的信号。

公开(公告)号：US20160072601A1

公开(公告)日：2016-03-10

申请号：US14483013

申请日：2014-09-10

Applicant: Silicon Image, Inc.

Inventor： Shrikant Ranade ,  Qian Yao ,  Lei Ming ,  Young IL Kim ,  Jiong Huang ,  Hoon Choi

IPC: H04J3/06 ,  H04J3/16 ,  H04L5/14

CPC classification number: H04J3/0602 ,  H04L5/14

Abstract: A system communicating over a full duplex control channel of a multimedia communication link by using synchronization signals that may also function as a logical link command. Synchronization indicators are exchanged between two communicating devices for maintaining synchronization of a logical link. At least two different types of synchronization signals may be sent between the two devices as synchronization indicators. A first synchronization signal is used by default to maintain synchronization of a logical link. A second synchronization signal is used in place of the first synchronization signal to maintain synchronization of the logical link. The second synchronization signal may be used to imply a virtual link command to indicate that a device is ready to receive data or has successfully received data over the virtual link.

Abstract translation: 通过使用也可以用作逻辑链路命令的同步信号在多媒体通信链路的全双工控制信道上进行通信的系统。 在两个通信设备之间交换同步指示符，以维持逻辑链路的同步。 可以在两个设备之间发送至少两种不同类型的同步信号作为同步指示符。 默认情况下使用第一同步信号来维持逻辑链路的同步。 使用第二同步信号代替第一同步信号以维持逻辑链路的同步。 第二同步信号可以用于暗示虚拟链路命令以指示设备准备好接收数据或已经通过虚拟链路成功接收到数据。

公开(公告)号：US09270607B2

公开(公告)日：2016-02-23

申请号：US14100328

申请日：2013-12-09

Applicant: Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

Inventor： Zdenek Chaloupka ,  James Aweya

IPC: H04J3/06 ,  H04L12/841 ,  H04L29/06 ,  H04L12/70 ,  H04J3/14

CPC classification number: H04L47/283 ,  H04J3/0602 ,  H04J3/0638 ,  H04J3/0661 ,  H04J3/0667 ,  H04J3/14 ,  H04L69/28 ,  H04L2012/5674

Abstract: This invention relates to packet selection techniques that can be used in conjunction with a clock recovery mechanism to mitigate the effects of packet delay variation on timing messages exchanged over a packet network, particularly when seeking to synchronize the time of a clock in a slave device to that of a master clock. The packet selection techniques can assist in reducing the noise in the recovered clock signal at the slave device, allowing recovery to a higher quality. Embodiments of the invention provide techniques based on extracting timing packets that create a constant interval between the arrival of selected packets at the slave device and on extracting timing packets which are closest to making the interval between arrival of the selected packets equal to the interval between the departure of the packets.

Abstract translation: 本发明涉及可以与时钟恢复机制一起使用的分组选择技术，以减轻分组延迟变化对在分组网络上交换的定时消息的影响，特别是当寻求将从设备中的时钟的时间同步到 一个主时钟。 分组选择技术可以帮助减少从设备恢复的时钟信号中的噪声，从而允许恢复到更高的质量。 本发明的实施例提供了基于提取在从设备的所选分组到达之间创建恒定间隔的定时分组的技术，以及提取最接近于使所选分组的到达之间的间隔等于所述分组之间的间隔的定时分组 包的离开

公开(公告)号：US20150381345A1

公开(公告)日：2015-12-31

申请号：US14315595

申请日：2014-06-26

Applicant: Synaptive Medical (Barbados) Inc.

Inventor： Monroe M. Thomas ,  Simon Alexander

IPC: H04L7/04 ,  H04L12/26 ,  H04J3/06

CPC classification number: H04L7/04 ,  H04J3/0602 ,  H04J3/0667 ,  H04L43/106

Abstract: An electronic device is provided including a processor, a communications interface coupled to the processor, a memory coupled to the processor, and a module saved in the memory. The module configures the processor to receive a first communications packet from a remote device via the communications interface including information useful for estimating a clock offset of the remote device, and determine an upper bound of the clock offset of the remote device with respect to the electronic device based on the information.

Abstract translation: 提供了一种电子设备，包括处理器，耦合到处理器的通信接口，耦合到处理器的存储器和保存在存储器中的模块。 该模块配置处理器以经由通信接口从远程设备接收包括对估计远程设备的时钟偏移有用的信息的第一通信分组，并确定远程设备相对于电子设备的时钟偏移的上限 设备基于该信息。

公开(公告)号：US09204405B2

公开(公告)日：2015-12-01

申请号：US14101116

申请日：2013-12-09

Applicant: Itron, Inc.

Inventor： Holger Hildebrandt ,  Keith W. Barnes ,  Bret Holmdahl ,  Jim Ogle

IPC: H04W56/00 ,  G01D4/00 ,  H04J3/06 ,  H04Q9/04 ,  H04W52/02

CPC classification number: H04W56/00 ,  G01D4/00 ,  H04J3/0602 ,  H04J3/0635 ,  H04Q9/04 ,  H04Q2209/60 ,  H04Q2209/845 ,  H04W52/0229

Abstract: Synchronization methods, apparatus and systems are disclosed. An example method includes storing, in memory of a device, schedule information indicating times at which the device is to listen for a sequential series of data frames, the schedule information further indicating a reference time at which transmission of the sequential series of data frames to the device is to be initiated; initiating a listening session at a first time of the schedule information according to a native clock of the device; identifying which of the data frames of the sequential series is received first during the listening session; and adjusting the native clock of the device based on the identified data frame.

Abstract translation: 公开了同步方法，装置和系统。 一种示例性方法包括在设备的存储器中存储指示设备要监听数据帧序列的时间的调度信息，该调度信息还指示连续数据帧的传输到 该设备将被启动; 根据设备的本机时钟在调度信息的第一时间发起监听会话; 识别在听觉会话期间首先接收到顺序序列的数据帧中的哪一个; 以及基于所识别的数据帧来调整设备的本机时钟。