公开(公告)号：US06199171B1

公开(公告)日：2001-03-06

申请号：US09105601

申请日：1998-06-26

申请人： Douglas Craig Bossen ,  Arun Chandra

发明人： Douglas Craig Bossen ,  Arun Chandra

IPC分类号： G06F1300

CPC分类号： G06F11/1695 ,  G06F11/1474 ,  G06F11/1497 ,  G06F11/1641 ,  G06F11/1691

摘要： A method and implementing system are provided for handling detected faults in a processor to improve reliability of a computer system. An exemplary fault-tolerant on-line transactional (OLT) computer system is illustrated which includes first and second OLT processors connected to an I/O processor through a system bus. Transaction results are stored in local processor buffers and at predetermined batch intervals, the stored transactions are compared. The matched transaction results are flushed to data store while unmatched transactions are re-executed. If the same errors do not occur during a re-execution, the errors are determined to be transient and the transaction results are flushed to storage.

摘要翻译： 提供了一种处理检测到的故障的方法和实现系统，以提高计算机系统的可靠性。 示出了示例性的容错在线事务（OLT）计算机系统，其包括通过系统总线连接到I / O处理器的第一和第二OLT处理器。 事务结果存储在本地处理器缓冲器中并且以预定的批间隔存储，所存储的事务被比较。 匹配的事务结果被刷新到数据存储，而不匹配的事务被重新执行。 如果在重新执行期间不会发生相同的错误，则将错误确定为暂时的，并将事务结果刷新到存储。

公开(公告)号：US06179207B2

公开(公告)日：2001-01-30

申请号：US08668049

申请日：1996-06-18

申请人： Douglas Craig Bossen ,  Chin-Long Chen ,  Fredrick Hayes Dill ,  Douglas Seymore Goodman ,  Mu-Yue Hsiao ,  Paul Vincent McCann ,  James Michael Mulligan ,  Ricky Allen Rand

发明人： Douglas Craig Bossen ,  Chin-Long Chen ,  Fredrick Hayes Dill ,  Douglas Seymore Goodman ,  Mu-Yue Hsiao ,  Paul Vincent McCann ,  James Michael Mulligan ,  Ricky Allen Rand

IPC分类号： G06K710

CPC分类号： G06K7/10861 ,  G06K1/126 ,  G06K7/0166 ,  G06K19/06028 ,  G06K2019/06253

摘要： A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

摘要翻译： 提供了具有固有的自身时钟特性的单宽度条形码，以便在非常大规模的集成电路制造工艺中的半导体晶片的识别中特别有用。 即使面对相对高的扫描速度变化，这里描述的代码是鲁棒的，可靠的和高度可读的。 这些代码在每个线性厘米的字符表示方面也是令人满意的，这在半导体制造中是重要的考虑因素，其中芯片和晶片上的空间是非常重要的。 另外，本发明的一个优选实施例在代码符号序列中显示相邻条之间的最大空格数的最小数目。

公开(公告)号：US06108753A

公开(公告)日：2000-08-22

申请号：US52457

申请日：1998-03-31

申请人： Douglas Craig Bossen ,  Manratha Rajasekharaiah Jaisimha ,  Avijit Saha ,  Shih-Hsiung Stephen Tung

发明人： Douglas Craig Bossen ,  Manratha Rajasekharaiah Jaisimha ,  Avijit Saha ,  Shih-Hsiung Stephen Tung

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F11/141 ,  G06F11/1064 ,  G06F12/0802 ,  G06F2201/81 ,  G06F2201/88

摘要： A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line. If the requested cache line still does not load from the L2 cache, the second level corrective methodology, after a selective number of retries, terminates and a machine check is generated to initiate a more extensive corrective or recovery action procedure. In an exemplary embodiment, a mechanism is illustrated for recovery from transient errors in an L1 cache load operation although the disclosed methodology may also be implemented partially or entirely in software and in any parity or other error detecting application.

摘要翻译： 提供了一种通过重试机制来增强纠错处理的方法和装置。 当检测到L1高速缓存指令行错误时，无论是通过奇偶校验错误检测过程还是通过ECC（纠错码）或其他过程，所公开的方法将调度导致线路错误的事件的自动重试，而不需要重新启动 整个系统。 此后，如果在经过预定次数的重试以从L1高速缓存加载所请求的数据之后仍存在错误，则进行第二级的校正动作。 第二级纠正措施包括访问备用存储器位置，例如L2缓存。 如果所请求的高速缓存行的状态是独占的或共享的，则生成人造L1小命令用于对所请求的高速缓存行启用L2访问。 如果请求的高速缓存行仍然不从L2高速缓存加载，则在选择性重试次数终止之后，第二级校正方法被生成，并且生成机器检查以启动更广泛的纠正或恢复操作过程。 在示例性实施例中，示出了用于从L1高速缓存加载操作中的瞬态错误中恢复的机制，尽管所公开的方法也可部分地或完全地以软件和任何奇偶校验或其他错误检测应用程序来实现。

公开(公告)号：US6058491A

公开(公告)日：2000-05-02

申请号：US929014

申请日：1997-09-15

申请人： Douglas Craig Bossen ,  Arun Chandra

发明人： Douglas Craig Bossen ,  Arun Chandra

IPC分类号： G06F11/16 ,  G06F13/00

CPC分类号： G06F11/1641 ,  G06F11/165 ,  G06F11/1695

摘要： A method and system for handling detected faults in a processor to improve reliability of a computer system is disclosed. A fault-tolerant computer system is provided which includes a first processor, a second processor, and a comparator. Coupled to a system bus, a first processor is utilized to produce a first output. The second processor, also coupled to the system bus, is utilized to produce a second output. During the operation of the computer system, the second processor operates at the same clock speed as the first processor and lags behind the first processor. The comparator is utilized to compare the first and second output such that an operation will be retried if the first output is not the same as the second output.

摘要翻译： 公开了一种用于处理处理器中检测到的故障以提高计算机系统的可靠性的方法和系统。 提供了一种包含第一处理器，第二处理器和比较器的容错计算机系统。 耦合到系统总线，利用第一处理器产生第一输出。 也耦合到系统总线的第二处理器用于产生第二输出。 在计算机系统的操作期间，第二处理器以与第一处理器相同的时钟速度运行并落在第一处理器之后。 比较器用于比较第一和第二输出，使得如果第一输出与第二输出不相同，则将重试操作。

公开(公告)号：US5956351A

公开(公告)日：1999-09-21

申请号：US834962

申请日：1997-04-07

申请人： Douglas Craig Bossen ,  Chin-Long Chen

发明人： Douglas Craig Bossen ,  Chin-Long Chen

IPC分类号： G06F12/16 ,  G06F11/10 ,  H03M13/09 ,  H03M13/11 ,  H03M13/00

CPC分类号： H03M13/098 ,  H03M13/11

摘要： A method of detecting errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller, by determining whether the encoding was performed using a first encoding method or a second encoding method, and thereafter decoding the data stream using a logic circuit based on a single parity-check matrix. The entire parity-check matrix is used to decode the data stream if the first encoding method was used, and a subset of the parity-check matrix is used to decode the data stream if the second encoding method was used. Encoding according to the first method allows correction of all single-symbol errors and detection of all double-symbol errors in the data stream, and encoding according to the second method allows correction of all single-bit errors and detection of all double-bit errors in the data stream. The subset matrix may be permuted if the second encoding method was used, to create a permuted matrix further allowing detection of single-symbol errors. In an exemplary embodiment, the parity-check matrix is a (76,66) matrix and the subset of the parity-check matrix is a (72,64) matrix.

摘要翻译： 一种检测在计算机系统中例如从存储器阵列传输到存储器控制器的数据流中的错误的方法，通过使用第一编码方法或第二编码方法确定编码是否被执行，然后对数据进行解码 使用基于单个奇偶校验矩阵的逻辑电路。 如果使用第一编码方法，则使用整个奇偶校验矩阵来解码数据流，并且如果使用第二编码方法，则使用奇偶校验矩阵的子集来解码数据流。 根据第一种方法的编码允许校正所有单符号错误和检测数据流中的所有双符号错误，并且根据第二种方法的编码允许校正所有单位错误并检测所有双位错误 在数据流中。 如果使用第二编码方法，子集矩阵可以被置换，以创建进一步允许检测单符号错误的置换矩阵。 在示例性实施例中，奇偶校验矩阵是（76,66）矩阵，并且奇偶校验矩阵的子集是（72,64）矩阵。