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    Identification of integrated circuits
    11.
    发明授权
    Identification of integrated circuits 有权
    集成电路识别

    公开(公告)号：US08788559B2

    公开(公告)日：2014-07-22

    申请号：US14095252

    申请日：2013-12-03

    Applicant: Empire Technology Development, LLC

    Inventor： Miodrag Potkonjak ,  Farinaz Koushanfar

    IPC: G06F17/12 ,  G06F17/11

    CPC classification number: G01R19/25 ,  G01R31/2851 ,  G06F15/00 ,  G06F21/73

    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification for an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.

    Abstract translation: 通常描述用于产生集成电路（IC）的识别号码的技术。 在一些示例中，用于产生IC的识别的方法可以包括选择IC的电路元件，评估用于所选择的电路元件的IC的属性的测量，其中各个测量与先前应用于IC的相应输入矢量相关联， 解决至少部分地基于针对所选择的电路元件的IC的属性的测量来确定所选择的电路元件的缩放因子并且变换所选择的电路元件的确定的缩放因子以产生 IC的识别号码。 还可以公开附加的变型和实施例。

    Efficient location discovery
    12.
    发明授权
    Efficient location discovery 有权

    公开(公告)号：US08712421B2

    公开(公告)日：2014-04-29

    申请号：US13728674

    申请日：2012-12-27

    Applicant: Empire Technology Development LLC

    Inventor： Miodrag Potkonjak

    IPC: H04W40/00

    CPC classification number: H04W4/023 ,  G01S5/0226 ,  G01S5/0242 ,  G01S5/0278 ,  G01S5/0289 ,  G01S5/14 ,  H04W16/24

    Abstract: Techniques are generally described for determining locations of a plurality of communication devices in a network. In some examples, methods for creating a location discovery infrastructure (LDI) for estimating locations of one or more of a plurality of communication nodes may comprise one or more of determining a plurality of locations in the terrain to place a corresponding plurality of beacon nodes, determining a plurality of beacon node groups for the placed beacon nodes, and determining a schedule for the placed beacon nodes to be active. Additional variants and embodiments are also disclosed.

    AUTONOMOUS, NON-INTERACTIVE, CONTEXT-BASED SERVICES FOR CELLULAR PHONE
    13.
    发明申请
    AUTONOMOUS, NON-INTERACTIVE, CONTEXT-BASED SERVICES FOR CELLULAR PHONE 有权
    自动，非互动，基于语音的蜂窝电话服务

    公开(公告)号：US20130303135A1

    公开(公告)日：2013-11-14

    申请号：US13941853

    申请日：2013-07-15

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Miodrag Potkonjak ,  Nathan Beckmann

    IPC: H04W4/16

    CPC classification number: H04W12/06 ,  G06Q20/3224 ,  H04L67/16 ,  H04M1/663 ,  H04M1/72552 ,  H04M1/72569 ,  H04W4/025 ,  H04W4/14 ,  H04W4/16 ,  H04W8/22 ,  H04W88/182

    Abstract: Embodiments include but are not limited to cellular phones, methods practice thereon, for autonomously servicing a call or a message, on behalf of the user, without interacting with the user, are disclosed herein. In various embodiments, data about a user of the cellular phone, internal conditions of the cellular phone, or external environment of the cellular phone are locally collected and from a wireless communication network. In various embodiments, multiple agents are provided to the cellular phone, wherein each agent is configured to determine, on receipt of a received call or message, a current service context based at least in part on some of the data stored, and autonomously servicing the received call or message based on the results of the determination. Other embodiments may be described and claimed.

    Abstract translation: 这里公开的实施例包括但不限于蜂窝电话，代表用户自主地服务呼叫或消息的方法实践，而不与用户交互。 在各种实施例中，关于蜂窝电话的用户，蜂窝电话的内部状况或蜂窝电话的外部环境的数据被本地收集并且从无线通信网络收集。 在各种实施例中，向蜂窝电话提供多个代理，其中每个代理被配置为至少部分地基于存储的一些数据来确定接收到所接收的呼叫或消息时的当前服务上下文，并且自主地维护 根据确定的结果收到呼叫或消息。 可以描述和要求保护其他实施例。

    COMBINED-MODEL DATA COMPRESSION
    14.
    发明申请
    COMBINED-MODEL DATA COMPRESSION 有权
    组合型数据压缩

    公开(公告)号：US20130282639A1

    公开(公告)日：2013-10-24

    申请号：US13923250

    申请日：2013-06-20

    Applicant: Empire Technology Development LLC

    Inventor： Miodrag Potkonjak

    IPC: G06N5/02

    CPC classification number: G06N5/02 ,  H03M7/30

    Abstract: Data compression technology (“the technology”) is disclosed that can employ two or more prediction models contemporaneously. The technology receives data from one or more sources; shifts or re-sample one of more corresponding signals; creates a prediction model of uncompressed samples using at least two different individual or composite models; selects a subset of the models for prediction of samples; determines an order in which signals will be compressed; formulates a combined predictions model using the selected subset of models; predicts a future value for the data using the combined compression model; defines a function that has as parameters at least the predicted future values for the data and actual values; selects a compression method for the values of the function; and compresses the data using at least the predicted value of the function.

    Abstract translation: 公开了可以同时使用两个或更多个预测模型的数据压缩技术（“技术”）。 该技术从一个或多个来源接收数据; 移位或重新采样更多相应信号之一; 使用至少两个不同的单个或复合模型创建未压缩样本的预测模型; 选择用于样本预测的模型的子集; 确定信号将被压缩的顺序; 使用所选择的模型子集制定组合预测模型; 使用组合压缩模型预测数据的未来值; 定义了至少具有数据和实际值的预测未来值的参数的函数; 为函数的值选择压缩方法; 并使用至少该功能的预测值来压缩数据。

    Hardware Synthesis Using Thermally Aware Scheduling And Binding
    15.
    发明申请
    Hardware Synthesis Using Thermally Aware Scheduling And Binding 有权
    使用热感知调度和绑定的硬件合成

    公开(公告)号：US20130145335A1

    公开(公告)日：2013-06-06

    申请号：US13751811

    申请日：2013-01-28

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Farinaz Koushanfar ,  Miodrag Potkonjak

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G06F17/5054 ,  G06F2217/16

    Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

    Abstract translation: 通常使用热感知调度和绑定来描述用于硬件合成的技术。 可以生成多个版本的硬件设计，每个版本具有日程表和绑定结果的变化。 可以执行调度和绑定，使得多个版本的热分布具有在这些版本之间较远的热峰。 这些版本的热峰之间物理距离的增加可以赋予版本独特的热特性。 可以构造设计的多个版本之间的旋转时间表，使得集成电路的热分布在操作期间平衡。 可以使用线性规划框架来分析多个设计并构建热感知旋转调度和绑定。 例如，可以选择K个最有效的版本，然后可以确定在旋转期间操作每个版本的持续时间。

    Scheduling and/or organizing task execution for a target computing platform
    18.
    发明授权
    Scheduling and/or organizing task execution for a target computing platform 有权
    为目标计算平台调度和/或组织任务执行

    公开(公告)号：US09471376B2

    公开(公告)日：2016-10-18

    申请号：US14171323

    申请日：2014-02-03

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Miodrag Potkonjak

    IPC: G06F9/46 ,  G06F9/48

    CPC classification number: G06F9/4881 ,  G06F9/4887 ,  G06F9/4893 ,  Y02D10/24

    Abstract: Techniques are generally described relating to methods, apparatuses and articles of manufactures for scheduling and/or organizing execution of tasks on a computing platform. In various embodiments, the method may include identifying successively one or more critical time intervals, and scheduling and/or organizing task execution for each of the one or more identified critical time intervals. In various embodiments, one or more tasks to be executed may be scheduled to execute based in part on their execution completion deadlines. In various embodiments, organizing one or more tasks to execute may include selecting a virtual operating mode of the platform using multiple operating speeds lying on a convexity energy-speed envelope of the platform. Intra-task delay caused by switching operating mode may be considered. Other embodiments may also be described and/or claimed.

    Abstract translation: 一般描述了关于在计算平台上调度和/或组织执行任务的制造商的方法，装置和物品的技术。 在各种实施例中，该方法可以包括连续地识别一个或多个关键时间间隔，以及针对所述一个或多个识别的关键时间间隔中的每一个调度和/或组织任务执行。 在各种实施例中，要执行的一个或多个任务可以部分地基于它们的执行完成期限来调度以执行。 在各种实施例中，组织要执行的一个或多个任务可以包括使用位于平台的凸起能量速度包络上的多个操作速度来选择平台的虚拟操作模式。 可以考虑由切换操作模式引起的任务内延迟。 其他实施例也可以被描述和/或要求保护。

    Yield optimization of processor with graphene-based transistors
    19.
    发明授权
    Yield optimization of processor with graphene-based transistors 有权
    具有石墨烯晶体管的处理器的产量优化

    公开(公告)号：US09411922B2

    公开(公告)日：2016-08-09

    申请号：US14414452

    申请日：2013-08-15

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Miodrag Potkonjak ,  Saro Meguerdichian

    IPC: G06F17/50 ,  H01L29/16 ,  H01L29/66 ,  H01L27/02

    CPC classification number: G06F17/5068 ,  G06F17/5009 ,  H01L27/0207 ,  H01L29/1606 ,  H01L29/66015

    Abstract: Techniques described herein generally include methods and systems related to the selection of a combination of graphene and non-graphene transistors in an IC design. To reduce the increase in leakage energy caused by graphene transistors, selected non-graphene transistors may be replaced with graphene transistors in the IC design while other non-graphene transistors may be retained in the IC design. To limit the number of graphene transistors in the IC design, graphene transistors may replace non-graphene transistors primarily at locations in the IC design where significant delay benefit can be realized.

    Abstract translation: 本文描述的技术通常包括与在IC设计中选择石墨烯和非石墨烯晶体管的组合相关的方法和系统。 为了减少由石墨烯晶体管引起的泄漏能量的增加，所选择的非石墨烯晶体管可以用IC设计中的石墨烯晶体管代替，而其他非石墨烯晶体管可以保留在IC设计中。 为了限制IC设计中的石墨烯晶体管的数量，石墨烯晶体管可以主要在IC设计中的位置处替代非石墨烯晶体，其中可以实现显着的延迟效益。

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