公开(公告)号：US20150006935A1

公开(公告)日：2015-01-01

申请号：US14300942

申请日：2014-06-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN ,  Kyung Jin BYUN ,  Nak Woong EUM

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.

Abstract translation: 公开了一种能够通过控制高速缓存的功率模式来降低高速缓存的功耗的处理器及其方法。 处理器可以包括处理器核心; 存储要在处理器核心中执行的指令的高速缓存; 以及高速缓存管理部，其基于指示根据在所述处理器核心中执行的算法确定的所述处理器核心的状态的处理器操作模式来控制所述高速缓存。 因此，可以降低高速缓存的功率消耗，并且可以通过考虑处理器的操作模式来控制高速缓存的功率模式来防止处理器核心性能的劣化。

公开(公告)号：US20140348250A1

公开(公告)日：2014-11-27

申请号：US14286822

申请日：2014-05-23

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Seunghyun CHO ,  Hyun Mi KIM ,  Kyung Jin BYUN ,  Nak Woong EUM

IPC: H04N19/80 ,  H04N19/46

CPC classification number: H04N19/86 ,  H04N19/423

Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.

Abstract translation: 提供了一种用于多个处理元件的滤波方法，用于对用于单帧图像的多个图像分区中的多个像素块进行滤波。 用于滤波像素块的方法包括：检查与图像分区边界相邻的第二边界像素块的状态，第二边界像素块是第二图像分区中的多个像素块中的一个，并且邻近第一边界像素块 第一图像分区，与图像分区边界相邻的第一边界像素块; 基于第二边界像素块的状态为第一边界像素块选择滤波区域; 并对第一边界像素块的滤波区域进行滤波。

公开(公告)号：US20130251043A1

公开(公告)日：2013-09-26

申请号：US13893386

申请日：2013-05-14

Applicant: Electronics and Telecommunications Research Institute

Inventor： Suk Ho LEE ,  Seong Mo PARK ,  Sang Heon LEE ,  Nak Woong EUM

IPC: H04N7/36

CPC classification number: H04N19/51 ,  H04N19/433 ,  H04N19/523

Abstract: A high-speed motion estimation method for estimating a motion of a picture at high speed in a high-speed motion estimation apparatus including an integer-times motion estimation unit and a decimal-times motion estimation unit. The integer-times motion estimation unit (1) receives pixel data of a picture for estimation of motion from an external frame memory, (2) stores pixel data of a current region in a current macroblock storage where multiple inputs/outputs are made, (3) stores pixel data of an estimation region in an estimation region macroblock storage of a sharable multiple input/output bank type, and (4) predicts an integer-times motion vector using both stored pixel data. The decimal-times motion estimation unit reads the pixel data of the estimation region from the estimation region macroblock storage which is sharable, and predicts a decimal-times motion vector using the read pixel data of the estimation region and the integer-times motion vector.

Abstract translation: 一种用于在包括整数运动估计单元和十进制运动估计单元的高速运动估计装置中估计高速图像运动的高速运动估计方法。 整数运动估计单元（1）从外部帧存储器接收用于运动估计的图像的像素数据，（2）存储当前区域的像素数据，该当前区域存在多个输入/输出的宏块存储器（ 3）将估计区域的像素数据存储在可共享的多输入/输出库类型的估计区域宏块存储器中，以及（4）使用两个存储的像素数据来预测整数倍的运动矢量。 十进制运动估计单元从可共享的估计区域宏块存储器中读取估计区域的像素数据，并使用估计区域和整数倍运动矢量的读取的像素数据预测十进制运动矢量。