公开(公告)号：US20150143045A1

公开(公告)日：2015-05-21

申请号：US14253466

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6022

Abstract: Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.

Abstract translation: 提供了一种用于减少未命中罚款的高速缓存控制装置和方法。 高速缓存控制装置包括被配置为将数据存储在存储器中的第一级高速缓存，连接到第一级高速缓存的第二级高速缓存，并且被配置为当第一级高速缓存不能根据数据请求调用数据时被处理器访问 指令，连接到第一和第二级高速缓存的预取缓冲器，并且被配置为将从第一和第二级别高速缓存传送的数据临时存储到核心，以及连接到第一级高速缓存的写缓冲器，并且被配置为接收地址信息和 第一级缓存的数据。

公开(公告)号：US20130238933A1

公开(公告)日：2013-09-12

申请号：US13785609

申请日：2013-03-05

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kyoung Seon SHIN

IPC: G06F11/27

CPC classification number: G06F11/27 ,  G06F11/2242 ,  G06F11/3648

Abstract: There present invention relates to a multi-core System On Chip (SoC) having a debugging function. The multi-core SoC having a debugging function includes one or more processors each configured to include an On Core Debug (OCD); a bus matrix configured to connect buses between the one or more processors and one or more peripheral devices; and a debug interface configured to include Processor Debug Interfaces (PDIs) for communicating with the respective OCDs and a Bus Debug Interface (BDI) for communicating with the bus matrix. In accordance with the present invention, the function of a multi-core SoC which has become complicated as compared with the existing singe core SoC may be efficiently verified.

Abstract translation: 本发明涉及具有调试功能的多核片上系统（SoC）。 具有调试功能的多核SoC包括一个或多个处理器，每个处理器被配置为包括On Core Debug（OCD）; 总线矩阵，被配置为在所述一个或多个处理器与一个或多个外围设备之间连接总线; 以及被配置为包括用于与各个OCD通信的处理器调试接口（PDI）和用于与总线矩阵通信的总线调试接口（BDI）的调试接口。 根据本发明，可以有效地验证与现有的单芯SoC相比变得复杂的多核SoC的功能。

公开(公告)号：US20150143049A1

公开(公告)日：2015-05-21

申请号：US14253349

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F12/0833

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract translation: 提供了一种缓存控制装置和方法，当多个处理器从芯片中的相同存储器读取程序时，保持数据的一致性和由高速缓存存储器生成的指令。 高速缓存控制装置包括：一致性控制器客户端，被配置为包括MESI寄存器，该MESI寄存器包括在指令高速缓存中，并且存储针对每行的修改状态，独占状态，共享状态和无效状态中的至少一个 指令高速缓存以及连接到一致性控制器并被配置为发送和接收广播地址信息，读取或写入信息以及将指向或从指令高速缓冲存储器中的另一个高速缓存的信息命中或丢失的一致性接口。

公开(公告)号：US20150006935A1

公开(公告)日：2015-01-01

申请号：US14300942

申请日：2014-06-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN ,  Kyung Jin BYUN ,  Nak Woong EUM

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.

Abstract translation: 公开了一种能够通过控制高速缓存的功率模式来降低高速缓存的功耗的处理器及其方法。 处理器可以包括处理器核心; 存储要在处理器核心中执行的指令的高速缓存; 以及高速缓存管理部，其基于指示根据在所述处理器核心中执行的算法确定的所述处理器核心的状态的处理器操作模式来控制所述高速缓存。 因此，可以降低高速缓存的功率消耗，并且可以通过考虑处理器的操作模式来控制高速缓存的功率模式来防止处理器核心性能的劣化。

公开(公告)号：US20170255520A1

公开(公告)日：2017-09-07

申请号：US15241808

申请日：2016-08-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young-Su KWON ,  Kyoung Seon SHIN ,  Kyung Jin BYUN ,  Nak Woong EUM

IPC: G06F11/10 ,  G06F12/0895 ,  G06F12/0804

CPC classification number: G06F11/1076 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/1032

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

公开(公告)号：US20140146884A1

公开(公告)日：2014-05-29

申请号：US13765263

申请日：2013-02-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Seung Hyun CHO ,  Hyun Mi KIM ,  Seong Mo PARK ,  Ig Kyun KIM ,  Kyoung Seon SHIN ,  Kyung Jin BYUN

IPC: H04N7/26

CPC classification number: H04N19/50 ,  H04N19/103 ,  H04N19/119 ,  H04N19/147 ,  H04N19/176 ,  H04N19/96

Abstract: The present invention provides a fast prediction mode determination method of a video encoder that may remove an unnecessary operation of an encoder by selectively terminating early or omitting a splitting process and a pruning process based on a probability distribution of rate-distortion values, and thereby enables the encoder to quickly determine a prediction mode. The present invention may include a method that may adaptively change a termination and omission determination criterion of the splitting process and the pruning process based on a characteristic of an input image. When using the method provided by the present invention, reliability regarding the termination and omission determination of the splitting process and the pruning process may be set and thus, it is possible to adjust the tradeoff between a decrease in an operation amount and a quality degradation of the encoder.

Abstract translation: 本发明提供了一种视频编码器的快速预测模式确定方法，其可以通过基于速率失真值的概率分布来选择性地终止或省略分离处理和修剪过程来选择性地终止编码器的不必要操作，从而使能 编码器快速确定预测模式。 本发明可以包括可以基于输入图像的特性自适应地改变分割处理和修剪处理的终止和省略确定标准的方法。 当使用本发明提供的方法时，可以设置关于分割处理和修剪过程的终止和省略确定的可靠性，因此可以调整操作量的降低和质量劣化之间的权衡 编码器。