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11.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING CONVERSION OF A MASK REGISTER INTO A VECTOR REGISTER. 审中-公开用于将掩码寄存器转换为矢量寄存器的系统，设备和方法。公开(公告)号：US20140223138A1
公开(公告)日：2014-08-07
申请号：US13992235
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Amit Gradstein , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Amit Gradstein , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a vector register in response to a single vector packed convert a mask register to a vector register instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法，用于响应于单向量压缩将掩码寄存器转换为向量寄存器，将掩码寄存器转换为向量寄存器指令，所述向量寄存器指令包括目的地向量寄存器操作数，源写入掩码 寄存器操作数和操作码。
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公开(公告)号：US20130283021A1
公开(公告)日：2013-10-24
申请号：US13976992
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Bret L. Toll , Mark J. Charney , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F9/30167 , G06F9/3802
摘要： An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.
摘要翻译： 描述了具有执行第一，第二，第三和第四指令的指令执行逻辑电路的装置。 第一指令和第二指令都将第一组输入向量元素插入到相应的第一和第二合成向量的多个第一非重叠部分之一中。 第一组具有第一位宽度。 多个第一非重叠部分中的每一个具有与第一组相同的位宽度。 第三指令和第四指令都将第二组输入矢量元素插入相应的第三和第四合成矢量的多个第二非重叠部分中的一个。 第二组具有大于所述第一位宽度的第二位宽度。 多个第二非重叠部分中的每一个具有与第二组相同的位宽度。 该装置还包括掩蔽层电路，以第一合成矢量粒度掩蔽第一和第三指令，并以第二合成向量粒度掩蔽第二和第四指令。
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公开(公告)号：US10565283B2
公开(公告)日：2020-02-18
申请号：US13976766
申请日：2011-12-22
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed.
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14.发明授权Systems, apparatuses, and methods for performing a double blocked sum of absolute differences 有权用于执行绝对差异的双重阻塞和的系统，装置和方法公开(公告)号：US09582464B2
公开(公告)日：2017-02-28
申请号：US13992229
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
CPC分类号： G06F9/3001 , G06F7/50 , G06F7/544 , G06F9/30036 , G06F9/3836 , G06F9/3877 , G06F15/78 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response to a single vector double block packed sum of absolute differences instruction that includes a destination vector register operand, first and second source operands, an immediate, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法的实施例响应于包括目的地向量寄存器操作数的绝对差指令的单向量双块压缩和，绝对差（SAD）的双块压缩和，第一和第二 描述源操作数，立即数和操作码。
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公开(公告)号：US20140208080A1
公开(公告)日：2014-07-24
申请号：US13997006
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Jesus Corbal , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30036
摘要： An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location.
摘要翻译： 描述了用于从源操作数到具有掩蔽的目的地操作数的下变频的装置和方法。 例如，根据一个实施例的方法包括以下操作：将从第一值下变频的源操作数值读取到下变换值并存储在目的位置; 读取存储在掩码寄存器中的每个掩码寄存器位，指示是否对源操作数值执行掩蔽操作或转换操作的掩码寄存器位; 如果屏蔽寄存器位指示要执行屏蔽操作，则执行指定的屏蔽操作并将掩蔽操作的结果存储在目的地位置中; 并且如果屏蔽寄存器位指示不执行屏蔽操作，则对源操作数值进行下变频并将下变频值存储在指定的目的地位置。
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16.发明申请公开(公告)号：US20130275727A1
公开(公告)日：2013-10-17
申请号：US13976580
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 方面的方法包括接收指令。 该指令指示整数步长，表示整数偏移，并指示目的地存储位置。 结果存储在目的地存储位置以响应该指令。 结果包括以数字顺序的至少四个整数的序列，其中至少四个整数中的最小的整数与零与整数偏移不同，并且具有与整数步长不同的连续位置中的序列的所有整数。 公开了其它方法，装置，系统和指令。
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公开(公告)号：US09639354B2
公开(公告)日：2017-05-02
申请号：US13977356
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
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18.发明申请公开(公告)号：US20140201502A1
公开(公告)日：2014-07-17
申请号：US13992236
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Elmoustapha Ould-Ahmed-Vall , Mostafa Hagog , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F17/142
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed butterfly horizontal cross add or subtract of packed data elements in response to a single vector packed butterfly horizontal cross add or subtract instruction that includes a destination vector register operand, a source vector register operand, an immediate, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行向量包装蝶形水平交叉加法或减法的系统，装置和方法响应于包括目的地向量寄存器操作数的单向量包装蝶式水平交叉加减法指令，源 描述向量寄存器操作数，立即数和操作码。
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19.发明申请Packed Data Rearrangement Control Indexes Generation Processors, Methods, Systems and Instructions 有权封装数据重排控制索引生成处理器，方法，系统和指令公开(公告)号：US20130283018A1
公开(公告)日：2013-10-24
申请号：US13977217
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30163 , G06F9/30167 , G06F9/3455
摘要： A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes generation instruction indicates a destination storage location. A result is stored in the destination storage location in response to the packed data rearrangement control indexes generation instruction. The result includes a sequence of at least four non-negative integers representing packed data rearrangement control indexes. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收打包数据重排控制索引生成指令。 打包数据重排控制索引生成指令表示目的地存储位置。 响应于打包数据重排控制索引生成指令，将结果存储在目的地存储位置中。 结果包括代表压缩数据重排控制指标的至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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20.发明申请Packed Data Rearrangement Control Indexes Precursors Generation Processors, Methods, Systems, and Instructions 有权封装数据重排控制索引前驱生成处理器，方法，系统和说明公开(公告)号：US20130275729A1
公开(公告)日：2013-10-17
申请号：US13977356
申请日：2011-12-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes the result including a sequence of at least four non-negative integers. In an aspect, values of the at least four non-negative integers are not calculated using a result of a preceding instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译： 一方面的方法包括接收指示目的地存储位置的指令。 结果存储在目的地存储位置以响应该指令。 结果包括结果，包括至少四个非负整数的序列。 在一个方面，使用前一条指令的结果不计算至少四个非负整数的值。 公开了其它方法，装置，系统和指令。
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