公开(公告)号：US09940170B2

公开(公告)日：2018-04-10

申请号：US13978949

申请日：2013-03-01

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5033 ,  G06F9/4856

Abstract: Technologies are generally provided for dynamically managing execution of sequential programs in a multi-core processing environment by dynamically hosting the data for the different dynamic program phases in the local caches of different cores. This may be achieved through monitoring data access patterns of a sequential program initially executed on a single core. Based on such monitoring, data identified as being accessed by different program phases may be sent to be stored in the local caches of different cores. The computation may then be moved from core to core based on which data is being accessed, when the program changes phase. Program performance may thus be enhanced by reducing local cache miss rates, proactively reducing the possibility of thermal hotspots, as well as by utilizing otherwise idle hardware.

公开(公告)号：US09804896B2

公开(公告)日：2017-10-31

申请号：US14128477

申请日：2013-06-11

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F9/46 ,  G06F9/50 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/5088 ,  G06F9/4856 ,  G06F11/3006 ,  G06F11/3433

Abstract: Techniques described herein are generally related to thread migration across processing cores of a multi-core processor. Execution of a thread may be migrated from a first processing core to a second processing core. Selective state data required for execution of the thread on the second processing core can be identified and can be dynamically acquired from the first processing core. The acquired state data can be utilized by the thread executed on the second processing core.

公开(公告)号：US09785568B2

公开(公告)日：2017-10-10

申请号：US14715114

申请日：2015-05-18

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F12/08 ,  G06F12/0897 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831 ,  G06F12/0808

CPC classification number: G06F12/0897 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/6046 ,  G06F2212/62 ,  Y02D10/13

Abstract: Techniques described herein are generally related to retrieval of data in computer systems having multi-level caches. The multi-level cache may include at least a first cache and a second cache. The first cache may be configured to receive a request for a cache line. The request may be associated with an instruction executing on a tile of the computer system. A suppression status of the instruction may be determined by a first cache controller to determine whether look-up of the first cache is suppressed based upon the determined suppression status. The request for the cache line may be forwarded to the second cache by the first cache controller after the look-up of the first cache is suppressed.

公开(公告)号：US20160026391A1

公开(公告)日：2016-01-28

申请号：US14648692

申请日：2013-12-04

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Sriram Vajapeyam

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0864 ,  G06F2212/6012 ,  G11C11/56 ,  G11C15/00 ,  Y02D10/13

Abstract: Techniques described herein are generally related to storing and retrieving data from a content-addressable memory (CAM). A data value to be stored in the CAM may be received, where the data value has two or more bits. The CAM may include a plurality of memory sets. An index corresponding to the data value may be determined. The index may be determined based on a subset of bits of the data value that correspond to an index bit set. A memory set of the CAM may be identified based on the determined index and the data value may be stored in a storage unit of the identified memory set.

Abstract translation: 本文描述的技术通常涉及从内容寻址存储器（CAM）存储和检索数据。 可以接收要存储在CAM中的数据值，其中数据值具有两个或更多位。 CAM可以包括多个存储器组。 可以确定与数据值对应的索引。 可以基于对应于索引位集合的数据值的位的子集来确定索引。 可以基于所确定的索引来识别CAM的存储器组，并且可以将数据值存储在所识别的存储器组的存储单元中。