公开(公告)号：US20070066367A1

公开(公告)日：2007-03-22

申请号：US10987720

申请日：2004-11-12

申请人： Jochen Kallscheuer ,  Bernhard Ruf ,  Reinhard Salchner ,  Helmut Schneider

发明人： Jochen Kallscheuer ,  Bernhard Ruf ,  Reinhard Salchner ,  Helmut Schneider

IPC分类号： A01D75/18 ,  G03C5/00 ,  A01F12/16 ,  A01F21/00

CPC分类号： G11C29/027 ,  G11C29/006 ,  G11C29/78 ,  H01L22/22 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods for repairing memory chips (7) with redundant cell areas and fuses using microlithography means, characterized by the following method steps: a) photoresist is applied to at least one wafer (6) which is to be repaired; b) a mask (1) is created in line with the chip-specific fuse coordinates; and c) at least one wafer (6) provided with photoresist is exposed using an exposure means through the mask (1); and an arrangement for a method for repairing memory chips (7) with redundant cell areas and fuses using microlithography means, where the arrangement comprises an application unit for photoresist onto wafers (6) which are to be repaired, a controllable mask (1) and an exposure means (2).

摘要翻译： 本发明涉及使用微光刻装置修复具有冗余单元区域和熔丝的存储器芯片（7）的方法，其特征在于以下方法步骤：a）将光致抗蚀剂施加到要修复的至少一个晶片（6）; b）根据芯片特定的熔丝坐标创建掩模（1）; 和c）使用曝光装置通过所述掩模（1）暴露设置有光致抗蚀剂的至少一个晶片（6）; 以及用于使用微光刻装置修复具有冗余单元区域和熔丝的存储器芯片（7）的方法的布置，其中所述布置包括用于光刻胶的应用单元，用于要修复的晶片（6）上，可控掩模（1）和 曝光装置（2）。

公开(公告)号：US20060156108A1

公开(公告)日：2006-07-13

申请号：US11287606

申请日：2005-11-28

申请人： Patric Stracke ,  Udo Hartmann ,  Jochen Kallscheuer

发明人： Patric Stracke ,  Udo Hartmann ,  Jochen Kallscheuer

IPC分类号： G01R31/28

CPC分类号： G01R31/31701 ,  G11C29/028 ,  G11C29/32 ,  G11C29/42 ,  G11C29/44

摘要： A method for testing semiconductor chips is disclosed. A chip to be tested has a test logic, at least one test mode is set in the form of a serial first bit string, the test modes are executed in the chip and test results or the status of the test modes are output from the chip in the form of a serial second bit string. The method includes at least one of the bit strings is provided with at least one binary check bit, the test logic being controlled by a check bit which is in a first logic state such that the bits of the bit string which follow the check bit are skipped until a check bit which is in the second logic state is detected by the test logic. The test logic is controlled by a check bit which is in the second logic state such that the bits of the bit string which follow the check bit are not skipped until a check bit which is in the first logic state is detected by the test logic.

摘要翻译： 公开了半导体芯片的测试方法。 要测试的芯片具有测试逻辑，至少一个测试模式以串行第一位串的形式设置，测试模式在芯片和测试结果中执行，或者测试模式的状态从芯片输出 以串行第二位串的形式。 该方法包括至少一个比特串被提供有至少一个二进制校验位，测试逻辑由处于第一逻辑状态的校验位控制，使得跟随校验位的位串的位是 跳过直到被测试逻辑检测到处于第二逻辑状态的校验位。 测试逻辑由处于第二逻辑状态的校验位控制，使得跟随校验位的位串的位不被跳过，直到被测试逻辑检测到处于第一逻辑状态的校验位。

公开(公告)号：US06728147B2

公开(公告)日：2004-04-27

申请号：US10202690

申请日：2002-07-24

申请人： Peter Beer ,  Jochen Kallscheuer ,  Gunnar Krause

发明人： Peter Beer ,  Jochen Kallscheuer ,  Gunnar Krause

IPC分类号： G11C700

CPC分类号： G11C29/12 ,  G11C29/10

摘要： A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.

摘要翻译： 用于片上测试集成存储器电路的单元阵列的存储单元的方法包括将不同的数据模式写入存储器单元并从存储器单元读取不同的数据模式以便测试存储器单元。 基本数据模式存储在数据字寄存器中，并通过应用由控制器提供的数据控制信号读出。 除了基本数据模式之外，通过使用数据控制信号，以目标方式访问与基本数据模式不同并存储在数据字寄存器部分中的至少一个另外的数据模式。 因此，测试迅速进行，并产生广泛的测试信息。