公开(公告)号：US20060156107A1

公开(公告)日：2006-07-13

申请号：US11287605

申请日：2005-11-28

申请人： Jochen Kallscheuer ,  Udo Hartmann ,  Patric Stracke

发明人： Jochen Kallscheuer ,  Udo Hartmann ,  Patric Stracke

IPC分类号： G01R31/28

CPC分类号： G01R31/31701 ,  G11C29/10 ,  G11C29/32

摘要： A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

摘要翻译： 公开了半导体芯片的测试方法。 在一个实施例中，要测试的芯片具有测试逻辑，设置至少一个测试模式，在芯片和测试结果中执行测试模式，或者从芯片输出测试模式的状态。 该方法包括提供具有至少一个具有多个寄存器的第一寄存器组和至少一个具有多个寄存器的第二寄存器组的芯片，第一寄存器组的至少一个寄存器和第二寄存器组的至少一个寄存器 以1：1逻辑结合。 在第一个寄存器组中存储第一个串行位串，其位序列可以分配给至少一个测试模式。 发送位序列以将第一寄存器组和第二寄存器组之间的逻辑组合应用于存储在第一寄存器组中的第一位串。 测试结果通过串行第二位串读出。

公开(公告)号：US07461308B2

公开(公告)日：2008-12-02

申请号：US11287605

申请日：2005-11-28

申请人： Jochen Kallscheuer ,  Udo Hartmann ,  Patric Stracke

发明人： Jochen Kallscheuer ,  Udo Hartmann ,  Patric Stracke

IPC分类号： G01R31/28

CPC分类号： G01R31/31701 ,  G11C29/10 ,  G11C29/32

摘要： A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the chip. The method includes providing a chip having at least one first register set having a plurality of registers and at least one second register set having a plurality of registers, at least one register of the first register set and at least one register of the second register set being 1:1 logically combined with one another. A first serial bit string is stored, the bit sequence of which can be assigned to at least one test mode, in the first register set. A bit sequence is transmitted for application of the logical combination between the first register set and the second register set to the first bit string stored in the first register set. The test results are read out by means of a serial second bit string.

摘要翻译： 公开了半导体芯片的测试方法。 在一个实施例中，要测试的芯片具有测试逻辑，设置至少一个测试模式，在芯片和测试结果中执行测试模式，或者从芯片输出测试模式的状态。 该方法包括提供具有至少一个具有多个寄存器的第一寄存器组和至少一个具有多个寄存器的第二寄存器组的芯片，第一寄存器组的至少一个寄存器和第二寄存器组的至少一个寄存器 以1：1逻辑结合。 在第一个寄存器组中存储第一个串行位串，其位序列可以分配给至少一个测试模式。 发送位序列以将第一寄存器组和第二寄存器组之间的逻辑组合应用于存储在第一寄存器组中的第一位串。 测试结果通过串行第二位串读出。

公开(公告)号：US20060156110A1

公开(公告)日：2006-07-13

申请号：US11288416

申请日：2005-11-29

申请人： Udo Hartmann ,  Jochen Kallscheuer ,  Patric Stracke

发明人： Udo Hartmann ,  Jochen Kallscheuer ,  Patric Stracke

IPC分类号： G01R31/28

CPC分类号： G11C29/46 ,  G11C2029/4402

摘要： A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

摘要翻译： 一种用于测试具有测试逻辑单元的半导体芯片的方法，包括：提供具有n个不同寄存器组的芯片，每个寄存器组具有m个不同的寄存器，每个寄存器被细分为每个具有n个寄存器的m个寄存器组，每个寄存器组分别仅具有一个单独寄存器 从寄存器集，m个寄存器组可以使用m个标头唯一标识; 通过用m个第一位字符串填充m个不同的寄存器组，每个位串分别分配给n个测试模式的状态; 发送至少一个头部以选择寄存器组和n个测试模式的状态并执行存储在所选择的寄存器组中的n个测试模式的状态; 并使用串行第二位串来读出测试结果或测试模式的状态。

公开(公告)号：US07454676B2

公开(公告)日：2008-11-18

申请号：US11288416

申请日：2005-11-29

申请人： Udo Hartmann ,  Jochen Kallscheuer ,  Patric Stracke

发明人： Udo Hartmann ,  Jochen Kallscheuer ,  Patric Stracke

IPC分类号： G01R31/28

CPC分类号： G11C29/46 ,  G11C2029/4402

摘要： A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

摘要翻译： 一种用于测试具有测试逻辑单元的半导体芯片的方法，包括：提供具有n个不同寄存器组的芯片，每个寄存器组具有m个不同的寄存器，每个寄存器被细分为每个具有n个寄存器的m个寄存器组，每个寄存器组分别仅具有一个单独寄存器 从寄存器集，m个寄存器组可以使用m个标头唯一标识; 通过用m个第一位字符串填充m个不同的寄存器组，每个位串分别分配给n个测试模式的状态; 发送至少一个头部以选择寄存器组和n个测试模式的状态并执行存储在所选择的寄存器组中的n个测试模式的状态; 并使用串行第二位串来读出测试结果或测试模式的状态。

公开(公告)号：US20060156108A1

公开(公告)日：2006-07-13

申请号：US11287606

申请日：2005-11-28

申请人： Patric Stracke ,  Udo Hartmann ,  Jochen Kallscheuer

发明人： Patric Stracke ,  Udo Hartmann ,  Jochen Kallscheuer

IPC分类号： G01R31/28

CPC分类号： G01R31/31701 ,  G11C29/028 ,  G11C29/32 ,  G11C29/42 ,  G11C29/44

摘要： A method for testing semiconductor chips is disclosed. A chip to be tested has a test logic, at least one test mode is set in the form of a serial first bit string, the test modes are executed in the chip and test results or the status of the test modes are output from the chip in the form of a serial second bit string. The method includes at least one of the bit strings is provided with at least one binary check bit, the test logic being controlled by a check bit which is in a first logic state such that the bits of the bit string which follow the check bit are skipped until a check bit which is in the second logic state is detected by the test logic. The test logic is controlled by a check bit which is in the second logic state such that the bits of the bit string which follow the check bit are not skipped until a check bit which is in the first logic state is detected by the test logic.

摘要翻译： 公开了半导体芯片的测试方法。 要测试的芯片具有测试逻辑，至少一个测试模式以串行第一位串的形式设置，测试模式在芯片和测试结果中执行，或者测试模式的状态从芯片输出 以串行第二位串的形式。 该方法包括至少一个比特串被提供有至少一个二进制校验位，测试逻辑由处于第一逻辑状态的校验位控制，使得跟随校验位的位串的位是 跳过直到被测试逻辑检测到处于第二逻辑状态的校验位。 测试逻辑由处于第二逻辑状态的校验位控制，使得跟随校验位的位串的位不被跳过，直到被测试逻辑检测到处于第一逻辑状态的校验位。

公开(公告)号：US06858447B2

公开(公告)日：2005-02-22

申请号：US10151990

申请日：2002-05-21

申请人： Udo Hartmann ,  Jochen Kallscheuer ,  Peter Beer

发明人： Udo Hartmann ,  Jochen Kallscheuer ,  Peter Beer

IPC分类号： G01R31/28 ,  G01R31/26 ,  G01R31/30 ,  G06F11/26 ,  G11C29/12 ,  G11C29/14 ,  G11C29/46 ,  H01L21/822 ,  H01L27/04 ,  H01L21/66 ,  G06F17/50

CPC分类号： G11C29/14 ,  G01R31/30 ,  G06F11/26 ,  G06F2201/83 ,  G11C29/46

摘要： A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.

摘要翻译： 描述了用于测试半导体芯片，特别是半导体存储器芯片的方法。 其中，在要测试的芯片中，至少设置一个测试模式，芯片中执行测试模式，芯片输出测试结果。 条件是，在设置之后和执行测试模式之前，执行检查模式，其中以定义的格式读出设置在芯片中的测试模式的状态。

公开(公告)号：US20060277379A1

公开(公告)日：2006-12-07

申请号：US11414554

申请日：2006-05-01

申请人： Fabien Funfrock ,  Jochen Kallscheuer ,  Michael Sommer ,  Christian Stocken

发明人： Fabien Funfrock ,  Jochen Kallscheuer ,  Michael Sommer ,  Christian Stocken

IPC分类号： G06F12/14 ,  G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/408

摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。

公开(公告)号：US07283419B2

公开(公告)日：2007-10-16

申请号：US11414554

申请日：2006-05-01

申请人： Fabien Funfrock ,  Jochen Kallscheuer ,  Michael Bernhard Sommer ,  Christian Stocken

发明人： Fabien Funfrock ,  Jochen Kallscheuer ,  Michael Bernhard Sommer ,  Christian Stocken

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/408

摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。

公开(公告)号：US06977516B2

公开(公告)日：2005-12-20

申请号：US10651803

申请日：2003-08-29

申请人： Jesus Ferreira ,  Jochen Kallscheuer

发明人： Jesus Ferreira ,  Jochen Kallscheuer

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention involves a semi-conductor component testing system, a process for semi-conductor components, as well as an assembly, more particularly a wafer with several semi-conductor components to be tested, whereby each semi-conductor component is allocated an individual identifying label, more particularly an identification-number, in order to perform the test—done individually for each semi-conductor component—on the respective semi-conductor component.

摘要翻译： 本发明涉及半导体部件测试系统，半导体部件的处理以及组件，更具体地说是具有要测试的几个半导体部件的晶片，由此每个半导体部件被分配个体识别 标签，更具体地说是一个识别号码，以便在相应的半导体部件上对每个半导体部件进行单独的测试。

公开(公告)号：US20050099201A1

公开(公告)日：2005-05-12

申请号：US10651803

申请日：2003-08-29

申请人： Jesus Ferreira ,  Jochen Kallscheuer

发明人： Jesus Ferreira ,  Jochen Kallscheuer

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention involves a semi-conductor component testing system, a process for semi-conductor components, as well as an assembly, more particularly a wafer with several semi-conductor components to be tested, whereby each semi-conductor component is allocated an individual identifying label, more particularly an identification-number, in order to perform the test—done individually for each semi-conductor component—on the respective semi-conductor component.