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    Method and arrangement for repairing memory chips using microlithography methods
    1.
    发明申请
    Method and arrangement for repairing memory chips using microlithography methods 审中-公开
    使用微光刻法修复存储芯片的方法和布置

    公开(公告)号：US20070066367A1

    公开(公告)日：2007-03-22

    申请号：US10987720

    申请日：2004-11-12

    申请人： Jochen Kallscheuer ,  Bernhard Ruf ,  Reinhard Salchner ,  Helmut Schneider

    发明人： Jochen Kallscheuer ,  Bernhard Ruf ,  Reinhard Salchner ,  Helmut Schneider

    IPC分类号： A01D75/18 ,  G03C5/00 ,  A01F12/16 ,  A01F21/00

    CPC分类号： G11C29/027 ,  G11C29/006 ,  G11C29/78 ,  H01L22/22 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to methods for repairing memory chips (7) with redundant cell areas and fuses using microlithography means, characterized by the following method steps: a) photoresist is applied to at least one wafer (6) which is to be repaired; b) a mask (1) is created in line with the chip-specific fuse coordinates; and c) at least one wafer (6) provided with photoresist is exposed using an exposure means through the mask (1); and an arrangement for a method for repairing memory chips (7) with redundant cell areas and fuses using microlithography means, where the arrangement comprises an application unit for photoresist onto wafers (6) which are to be repaired, a controllable mask (1) and an exposure means (2).

    摘要翻译： 本发明涉及使用微光刻装置修复具有冗余单元区域和熔丝的存储器芯片（7）的方法，其特征在于以下方法步骤：a）将光致抗蚀剂施加到要修复的至少一个晶片（6）; b）根据芯片特定的熔丝坐标创建掩模（1）; 和c）使用曝光装置通过所述掩模（1）暴露设置有光致抗蚀剂的至少一个晶片（6）; 以及用于使用微光刻装置修复具有冗余单元区域和熔丝的存储器芯片（7）的方法的布置，其中所述布置包括用于光刻胶的应用单元，用于要修复的晶片（6）上，可控掩模（1）和 曝光装置（2）。

    Electromechanical motor
    5.
    发明授权
    Electromechanical motor 失效
    机电电机

    公开(公告)号：US07759841B2

    公开(公告)日：2010-07-20

    申请号：US12416683

    申请日：2009-04-01

    申请人： Helmut Schneider ,  Güido Schmid ,  Thomas Trietz ,  Vladimir Popov

    发明人： Helmut Schneider ,  Güido Schmid ,  Thomas Trietz ,  Vladimir Popov

    IPC分类号： H01L41/08

    CPC分类号： H02N2/04

    摘要： The invention relates to an electromechanical motor having a stator that has a drive unit and a frame component in which the drive unit is held, and a sliding element that is constructed such that, actuated by the drive unit, it performs a movement with respect to the stator in a direction of translation, wherein the drive unit has at least one electromechanical drive element that extends in the direction of translation and a power transmission element that is constructed so as to transmit a movement of the drive element to the sliding element. The sliding element has a supporting component and a drive rail, the drive rail extending in the direction of translation and interacting with the power transmission element and the drive rail being held at both its end faces in the supporting component, and between the supporting component and the frame component of the stator, there is a bearing for supporting the sliding element in the frame component.

    摘要翻译： 本发明涉及具有定子的机电马达，该定子具有驱动单元和保持驱动单元的框架部件，以及构造成由驱动单元致动的滑动元件，其相对于 所述定子在平移方向上，其中所述驱动单元具有至少一个在平移方向上延伸的机电驱动元件，以及构造成将所述驱动元件的运动传递到所述滑动元件的动力传递元件。 滑动元件具有支撑部件和驱动轨道，驱动轨道在平移方向上延伸并且与动力传递元件相互作用，并且驱动轨道保持在支撑部件的两端面以及支撑部件和 定子的框架部件存在用于将滑动元件支撑在框架部件中的轴承。

    Semiconductor Memory and Method for Operating a Semiconductor Memory
    6.
    发明申请
    Semiconductor Memory and Method for Operating a Semiconductor Memory 有权
    用于操作半导体存储器的半导体存储器和方法

    公开(公告)号：US20090285006A1

    公开(公告)日：2009-11-19

    申请号：US12125684

    申请日：2008-05-22

    申请人： Roland Thewes ,  Michael Otto ,  Helmut Schneider

    发明人： Roland Thewes ,  Michael Otto ,  Helmut Schneider

    IPC分类号： G11C5/06 ,  G11C7/00

    CPC分类号： G11C11/4094 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

    摘要： A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier.

    摘要翻译： 半导体存储器具有多个读取放大器，其中两个互补位线中的每一个被连接到其上，其中半导体存储器包括用于每个位线的至少一个开关元件，通过该至少一个开关元件，位线的至少部分部分可以 与读取放大器电耦合，并且其中半导体存储器控制第一开关元件，使得第一开关元件在读出和/或刷新连接到位线的任何存储单元时暂时将至少部分部分断电 来自读取放大器的位线。

    SENSE-AMPLIFIER CIRCUIT FOR A MEMORY DEVICE WITH AN OPEN BIT LINE ARCHITECTURE
    7.
    发明申请
    SENSE-AMPLIFIER CIRCUIT FOR A MEMORY DEVICE WITH AN OPEN BIT LINE ARCHITECTURE 失效
    用于具有开放位线架构的存储器件的感测放大器电路

    公开(公告)号：US20090097347A1

    公开(公告)日：2009-04-16

    申请号：US11872573

    申请日：2007-10-15

    申请人： Martin Versen ,  Helmut Schneider

    发明人： Martin Versen ,  Helmut Schneider

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/4099

    摘要： A device for accessing a logical content of a memory cell, the memory cell including a cell capacity for storing a charge related to the logical content, wherein the cell capacity is connected between a bit line having a bit line capacity and a reference potential, the device including: a reference node having a reference capacity being smaller than the bit line capacity; and a circuit for changing a potential of the bit line and the reference node, respectively, in case of a read or write access of the memory cell, wherein the change of the potential of the bit line is conducted with a first current and the change of the potential of the reference node is conducted with a second current, wherein the first current is greater than the second current.

    摘要翻译： 一种用于访问存储器单元的逻辑内容的设备，所述存储单元包括用于存储与所述逻辑内容相关的电荷的单元容量，其中所述单元容量连接在具有位线容量的位线和参考电位之间， 该装置包括：具有小于所述位线容量的参考容量的参考节点; 以及用于在存储单元的读取或写入访问的情况下分别改变位线和参考节点的电位的电路，其中，利用第一电​​流进行位线的电位变化，并且改变 参考节点的电位用第二电流进行，其中第一电流大于第二电流。

    Integrated Circuit
    8.
    发明申请
    Integrated Circuit 有权
    集成电路

    公开(公告)号：US20090085644A1

    公开(公告)日：2009-04-02

    申请号：US12234398

    申请日：2008-09-19

    申请人： Harald Roth ,  Helmut Schneider

    发明人： Harald Roth ,  Helmut Schneider

    IPC分类号： H03K17/284 ,  H03K17/687

    CPC分类号： G11C11/4074 ,  G11C7/08 ,  G11C11/4091 ,  G11C2207/005 ,  H03K19/018521

    摘要： An integrated circuit includes an input terminal for applying an input signal, a further input terminal for applying a further input signal having a level differing from the level of the initial input signal, an output terminal for providing an output signal, a switching unit having a controllable switch, which is arranged between the input terminal and the output terminal, and a further switching unit, which is arranged between the further input terminal and the output terminal. The integrated circuit is operated in a first and subsequent second operating state. The controllable switch of the switching unit is controlled to be conductive in the first and second operating state. In the first operating state, the output signal is provided in dependence on the level of the input signal, and in the second operating state in dependence on the level of the second input signal.

    摘要翻译： 集成电路包括用于施加输入信号的输入端子，用于施加具有与初始输入信号的电平不同的电平的另外的输入信号的另外的输入端子，用于提供输出信号的输出端子，具有输入信号的开关单元 布置在输入端子和输出端子之间的可控开关，以及设置在另一个输入端子和输出端子之间的另一个开关单元。 集成电路在第一和随后的第二操作状态下操作。 开关单元的可控开关在第一和第二操作状态下被控制为导通。 在第一操作状态下，根据输入信号的电平，根据第二输入信号的电平在第二操作状态下提供输出信号。

    INTEGRATED CIRCUIT AND METHOD FOR CHARGE REVERSAL OF A CIRCUIT PART OF THE INTEGRATED CIRCUIT
    9.
    发明申请
    INTEGRATED CIRCUIT AND METHOD FOR CHARGE REVERSAL OF A CIRCUIT PART OF THE INTEGRATED CIRCUIT 有权
    集成电路的集成电路和电路逆变器的方法

    公开(公告)号：US20090009003A1

    公开(公告)日：2009-01-08

    申请号：US12168747

    申请日：2008-07-07

    申请人： Harald Roth ,  Helmut Schneider

    发明人： Harald Roth ,  Helmut Schneider

    IPC分类号： H02J1/00

    CPC分类号： G11C8/08 ,  G11C11/4085 ,  Y10T307/675

    摘要： A description is given of a method for charge reversal of a circuit part of an integrated circuit from a first electrical potential to a second electrical potential of a first voltage network. In this case, the circuit part is connected to the first voltage network for charge reversal. Furthermore, the circuit part is connected to a second voltage network for charge reversal, said second voltage network providing a third electrical potential between the first and the second electrical potential. The circuit part is automatically isolated from the second voltage network before its electrical potential reaches the second electrical potential.

    摘要翻译： 给出了对集成电路的电路部分从第一电压网络的第一电位到第二电位的电荷反转的方法的描述。 在这种情况下，电路部分连接到第一电压网络进行充电反转。 此外，电路部分连接到用于电荷反向的第二电压网络，所述第二电压网络在第一和第二电位之间提供第三电位。 电路部分在其电位达到第二电位之前自动与第二电压网络隔离。

    Device and method for regulating the threshold voltage of a transistor
    10.
    发明申请
    Device and method for regulating the threshold voltage of a transistor 有权
    用于调节晶体管的阈值电压的装置和方法

    公开(公告)号：US20070008796A1

    公开(公告)日：2007-01-11

    申请号：US11477077

    申请日：2006-06-28

    申请人： Jens Egerer ,  Rainer Bartenschlager ,  Helmut Schneider

    发明人： Jens Egerer ,  Rainer Bartenschlager ,  Helmut Schneider

    IPC分类号： G11C7/04 ,  G11C7/06 ,  G11C5/14

    CPC分类号： G11C7/08 ,  G11C7/04 ,  G11C7/06

    摘要： A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

    摘要翻译： 公开了一种用于调节晶体管的阈值电压的方法和装置。 该器件包括电路，其被配置为修改在晶体管的体连接处施加的电压，使得晶体管的阈值电压至少在第一温度范围内基本上与温度无关。 在一个实施例中，器件包括存储器件，晶体管是存储器件的读出放大器的晶体管。