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公开(公告)号：US07698664B2
公开(公告)日：2010-04-13
申请号：US11751511
申请日：2007-05-21
CPC分类号： G06Q40/04 , H04L9/0838 , H04L2209/16
摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.
摘要翻译： 这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。 被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。 可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。 例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。 可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。 然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。 例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。 可能会生成错误报告，而不会泄露安全规则。
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公开(公告)号：US20100023905A1
公开(公告)日：2010-01-28
申请号：US12390354
申请日：2009-02-20
申请人： Fedor G. Pikus , John W. Stedman
发明人： Fedor G. Pikus , John W. Stedman
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A layout design for a portion of a microdevice design is partitioned into sections or “bins.” Next, a critical area value is estimated for one or more of the bins. One or more of these estimated bins is then selected for a more detailed analysis. After the estimated bins have been selected, a detailed critical area analysis of the selected bins is performed. Once the actual critical area for each of the estimated bins has been determined, the actual critical areas for selected estimated bins are correlated with those bin's corresponding estimated values. By correlating the actual critical areas of selected estimated bin to those bin's corresponding estimated values, a mapping function can be determined. After the mapping function has been determined, it is applied to the estimated values for each of the remaining bins of the layout design (i.e., the bins for which an actual critical area have not yet been determined) to obtain critical area information for the layout design. The layout design can then be modified based upon the obtained critical area information.
摘要翻译： 微型设计设计的一部分的布局设计被划分为部分或“仓”。 接下来，估计一个或多个箱的临界面积值。 然后选择一个或多个这些估计的箱体进行更详细的分析。 在选择了估计的料仓之后，对所选择的料仓进行详细的关键区域分析。 一旦确定了每个估计仓的实际临界区域，则所选估计仓的实际关键区域与这些仓库的相应估计值相关。 通过将所选择的估计bin的实际关键区域与这些bin的相应估计值相关联，可以确定映射函数。 在确定映射函数之后，将其应用于布局设计的每个剩余箱的估计值（即，尚未确定实际临界区的箱），以获得布局的关键区域信息 设计。 然后可以基于获得的关键区域信息来修改布局设计。
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公开(公告)号：US20090222927A1
公开(公告)日：2009-09-03
申请号：US12226943
申请日：2007-04-30
申请人： Fedor G. Pikus
发明人： Fedor G. Pikus
CPC分类号： G06F17/5081 , G06F21/6209 , G06F21/6227 , G09C5/00 , H04L9/0863 , H04L9/321
摘要： In one exemplary embodiment disclosed herein, an electronic design automation tool may receive information related to electronic design automation that contains secured information, such as physically secured information, and annotations to indicate the secured portions of the information. Upon receiving such information, the electronic design automation tool may identify those portions of the information comprising secured information related to electronic design automation, and unlock the secured information for processing. The electronic design automation tool may process at least some of the secured electronic design automation information without revealing that secured information to unauthorized persons, tools, systems, or otherwise compromising the protection of that secured information. That is, the design automation tool may process the secured electronic design automation information so that the secured information is concealed both while it is being processed and by the output information generated from processing the secured information.
摘要翻译： 在本文公开的一个示例性实施例中，电子设计自动化工具可以接收与电子设计自动化相关的信息，其包含诸如物理上保密的信息等安全信息，以及指示信息的安全部分的注释。 电子设计自动化工具在接收到这样的信息时，可以识别包括与电子设计自动化相关的安全信息的信息的那些部分，并且解锁用于处理的安全信息。 电子设计自动化工具可以处理至少一些安全的电子设计自动化信息，而不向未经授权的人员，工具，系统或其他方式泄漏安全信息，从而损害对该安全信息的保护。 也就是说，设计自动化工具可以处理安全的电子设计自动化信息，使得安全信息在被处理时被隐藏，并且由处理安全信息产生的输出信息。
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公开(公告)号：US20080189667A1
公开(公告)日：2008-08-07
申请号：US11986564
申请日：2007-11-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.
摘要翻译： 模拟设计规则检查工具分析微设计设计，例如集成电路设计，以识别共享指定关系的几何元素的出现。 当工具识别这些几何元素的这种出现时，它将将这些几何元素相关联或“聚集”到一个可识别的单元中。 对于几何元素的特定“簇”，模拟设计规则检查工具将确定用户所需的测量值或测量值。 一旦模拟设计规则检查工具确定了必要的测量值，它将使用这些值来评估描述模型的功能。
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公开(公告)号：US09652574B2
公开(公告)日：2017-05-16
申请号：US13093828
申请日：2011-04-25
CPC分类号： G06F17/5072 , G03F1/44 , G06F17/5045 , G06F17/5068 , G06F2217/12 , H01L27/0207 , Y02P90/265
摘要： Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.
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公开(公告)号：US20120266117A1
公开(公告)日：2012-10-18
申请号：US13532484
申请日：2012-06-25
申请人： Fedor G. Pikus , Kobi Kresh
发明人： Fedor G. Pikus , Kobi Kresh
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F17/5081
摘要： A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object.
摘要翻译： 一种减少电路列表的技术。 根据该技术的示例，分析电路列表的至少一部分以识别由多个电路部件组成的电路结构的出现。 对于定义的电路结构的每个识别的出现，对应于多个分量创建注入数据对象，并且将注入数据对象替换为电路列表的部分来代替多个分量。 对于定义结构的每次出现，可以由相应的注入数据对象确定并包含所定义结构的出现的一个或多个属性。
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公开(公告)号：US08225246B2
公开(公告)日：2012-07-17
申请号：US12719981
申请日：2010-03-09
申请人： Fedor G. Pikus , Kobi Kresh
发明人： Fedor G. Pikus , Kobi Kresh
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F17/5081
摘要： A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object.
摘要翻译： 一种减少电路列表的技术。 根据该技术的示例，分析电路列表的至少一部分以识别由多个电路部件组成的电路结构的出现。 对于定义的电路结构的每个识别的出现，对应于多个分量创建注入数据对象，并且将注入数据对象替换为电路列表的部分来代替多个分量。 对于定义结构的每次出现，可以由相应的注入数据对象确定并包含所定义结构的出现的一个或多个属性。
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18.发明申请公开(公告)号：US20110145772A1
公开(公告)日：2011-06-16
申请号：US12780785
申请日：2010-05-14
申请人： Fedor G. Pikus
发明人： Fedor G. Pikus
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/12
摘要： A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for performing one or more desired electronic design automation operations. The platform may also provide export modules and import modules. An export module extracts relevant data from the database, and configures that data for use by a specific electronic design automation operation execution module. An import module then receives output data from a particular electronic design automation operation execution module, configures that data for integration into the unified database, and then imports the configured data into the database.
摘要翻译： 用于分析和验证集成电路设计的模块化电子设计自动化工具平台。 平台可以提供单个统一的数据库，其可以包含与集成电路设计相关的逻辑信息和物理信息，以及用于执行一个或多个期望的电子设计自动化操作的多个电子设计自动化操作执行模块。 该平台还可以提供导出模块和导入模块。 导出模块从数据库中提取相关数据，并配置数据供特定电子设计自动化操作执行模块使用。 然后，导入模块从特定的电子设计自动化操作执行模块接收输出数据，将数据配置为统一数据库，然后将配置的数据导入数据库。
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公开(公告)号：US20100199107A1
公开(公告)日：2010-08-05
申请号：US12758640
申请日：2010-04-12
CPC分类号： G06Q40/04 , H04L9/0838 , H04L2209/16
摘要： Described herein are methods and systems for secure exchange of information related to electronic design automation. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information may be provided to an electronic design automation tool for processing without revealing at least some of the secured information. For instance, rule files related to integrated circuit manufacturability may be selectively annotated to indicate portions thereof deserving of protection. An encryption tool may be used to secure the information so indicated and generate a file comprising secured information related to electronic design automation. An electronic design automation tool may then unlock and use the secured information without revealing the same. For instance, the tool may be a physical verification tool capable of verifying whether any of the one or more integrated circuit layouts may violate one or more of the secured rules. An error report may be generated without revealing the secured rules.
摘要翻译： 这里描述了用于安全地交换与电子设计自动化相关的信息的方法和系统。 被视为敏感而其他值得保护的信息可以通过加密，混淆和其他安全措施等方法来保护。 可以将安全信息提供给电子设计自动化工具用于处理，而不暴露至少一些安全信息。 例如，可以选择性地注释与集成电路可制造性相关的规则文件，以指示其应得到保护的部分。 可以使用加密工具来保护所指示的信息，并生成包括与电子设计自动化有关的安全信息的文件。 然后，电子设计自动化工具可以解锁和使用安全信息，而不会泄露它们。 例如，该工具可以是能够验证一个或多个集成电路布局中的任一个是否可能违反一个或多个安全规则的物理验证工具。 可能会生成错误报告，而不会泄露安全规则。
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公开(公告)号：US20100185995A1
公开(公告)日：2010-07-22
申请号：US12541906
申请日：2009-08-14
申请人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
发明人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
摘要翻译： 用于有效地确定互连线是否具有低于最大规定值的阻抗分量值的技术。 使用指定的最大阻抗分量值来限制通过寄生提取分析过程分析的互连线的数量。 基于互连线的特性和指定的最大阻抗分量值创建分析窗口。 窗口的大小对应于具有指定的最大阻抗分量值的互连线的最小长度。 一旦创建了分析窗口，就检查互连线以确定它们中的任何一个是否到达（或超出）分析窗口，从而可以识别出超过规定的最大阻抗分量值的互连线。 如果通过使用分析窗口还没有确定剩余的互连线未被确定为超过规定的最大阻抗分量值，那么这些剩余互连线的阻抗分量值可以使用寄生提取处理来具体确定。
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