公开(公告)号：US20030107394A1

公开(公告)日：2003-06-12

申请号：US10326423

申请日：2002-12-19

Applicant: FormFactor, Inc.

Inventor： Igor Y. Khandros ,  David V. Pedersen

IPC: G01R031/26

CPC classification number: G01R31/2886 ,  G01R31/287 ,  G01R31/2874 ,  G01R31/318511 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs. A significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller and promulgating these signals over the relatively many interconnections between the ASICs and the DUTs. The ASICs can also generate at least a portion of these signals in response to control signals from the host controller. Physical alignment techniques are also described. Micromachined indentations on the front surface of the ASICs ensure capturing free ends of the spring contact elements. Micromachined Features on the back surface of the ASICs and the front surface of the interconnection substrate to which they are mounted facilitate precise alignment of a plurality of ASICs on the support substrate.

Abstract translation: 用于执行半导体器件的晶片级老化和测试的技术包括具有有源电子部件的测试基板，例如安装到互连基板或并入其中的ASIC，实现ASIC和多个器件之间的互连的金属弹簧接触元件 在测试晶片（WUT）上的测试（DUT）都被置于真空容器中，使得ASIC可以在与DUT的老化温度无关并且显着低于DUT的老化温度的温度下工作。 弹簧接触元件可以被安装到DUT或ASIC上，并且可以扇出来放松对ASIC和DUT的对准和互连的容限约束。 由于ASIC能够通过相对较少的来自主机控制器的信号线接收用于测试DUT的多个信号，并且在这些信号之间的相对多的互连上发布这些信号，因此实现了互连计数的显着减少和互连基板的随后简化。 ASIC和DUT。 ASIC还可以响应于来自主机控制器的控制信号而产生这些信号的至少一部分。 还描述了物理对准技术。 ASIC的前表面上的微加工凹口确保捕获弹簧接触元件的自由端。 ASIC的后表面上的微加工特征和它们所安装的互连基板的前表面有助于精确地对准支撑基板上的多个ASIC。

公开(公告)号：US20030057975A1

公开(公告)日：2003-03-27

申请号：US10202971

申请日：2002-07-25

Applicant: FormFactor, Inc.

Inventor： Mohammad Eslamy ,  David V. Pedersen ,  Harry D. Cobb

IPC: G01R031/02

CPC classification number: G01R31/2886 ,  G01R3/00 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49171 ,  Y10T29/49178 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.