公开(公告)号：US20120142154A1

公开(公告)日：2012-06-07

申请号：US13354579

申请日：2012-01-20

申请人： FUJIO MASUOKA ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： FUJIO MASUOKA ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： An SGT production method includes forming a pillar-shaped first-conductive-type semiconductor layer and forming a second-conductive-type semiconductor layer underneath the first-conductive-type semiconductor layer. A dummy gate dielectric film and a dummy gate electrode are formed around the first-conductive-type semiconductor layer and a first dielectric film is formed on an upper region of a sidewall of the first-conductive-type semiconductor layer in contact with a top of the gate electrode. A first dielectric film is formed on a sidewall of the gate electrode and a second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer. A second-conductive-type semiconductor layer is formed in an upper portion of the first-conductive-type semiconductor layer and a metal-semiconductor compound is formed on each of the second-conductive-type semiconductor layers. The dummy gate dielectric film and the dummy gate electrode are removed and a high-k gate dielectric film and a metal gate electrode are formed.

摘要翻译： SGT制造方法包括形成柱状的第一导电型半导体层，在第一导电型半导体层的下方形成第二导电型半导体层。 在第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极，并且第一电介质膜形成在第一导电型半导体层的与顶部接触的第一导电型半导体层的侧壁的上部区域 栅电极。 第一电介质膜形成在栅电极的侧壁上，第二导电型半导体层形成在第一导电型半导体层的上部。 第二导电型半导体层形成在第一导电型半导体层的上部，并且在每个第二导电型半导体层上形成金属半导体化合物。 除去虚拟栅极电介质膜和虚拟栅电极，形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US08163605B2

公开(公告)日：2012-04-24

申请号：US12704004

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode.

摘要翻译： 旨在提供一种能够获得用于降低源极，漏极和栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及要获得的柱状半导体的期望直径的结构的SGT制造方法。 该方法包括以下步骤：形成柱状第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极电极的顶部接触的第一电介质膜，通过栅极电介质膜形成; 在所述栅电极的侧壁上形成第一电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层的上部和下方的每个第二导电型半导体层上形成金属 - 半导体化合物; 去除伪栅极电介质膜和伪栅电极并形成高k栅极电介质膜和金属栅电极。

公开(公告)号：US20100219464A1

公开(公告)日：2010-09-02

申请号：US12703991

申请日：2010-02-11

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/458 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642

摘要： Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 公开了一种半导体器件制造方法，其包括以下步骤：在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在所述柱状的第一导电型半导体层周围形成具有金属膜和非晶硅或多晶硅膜的叠层结构的栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成第一和第二侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成金属 - 半导体化合物; 在栅电极上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成接触; 并且在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成接触。

公开(公告)号：US20100207199A1

公开(公告)日：2010-08-19

申请号：US12704000

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L29/78 ,  H01L21/66

CPC分类号： H01L29/78642 ,  H01L22/26

摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。

公开(公告)号：US20100187600A1

公开(公告)日：2010-07-29

申请号：US12699611

申请日：2010-02-03

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US08395208B2

公开(公告)日：2013-03-12

申请号：US13478359

申请日：2012-05-23

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US08241976B2

公开(公告)日：2012-08-14

申请号：US12704000

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/8232

CPC分类号： H01L29/78642 ,  H01L22/26

摘要： The method includes the steps of: forming a planar semiconductor layer on an oxide film formed on a substrate and then forming a pillar-shaped first-conductive-type semiconductor layer on the planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode made of a metal, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming a sidewall-shaped dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 该方法包括以下步骤：在形成在基板上的氧化膜上形成平面半导体层，然后在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在柱状的第一导电型半导体层周围形成栅极电介质膜和由金属制成的栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层。

公开(公告)号：US08158468B2

公开(公告)日：2012-04-17

申请号：US12703991

申请日：2010-02-11

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Tomohiko Kudo ,  Shintaro Arai

IPC分类号： H01L21/8232 ,  H01L29/786

CPC分类号： H01L29/458 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/78618 ,  H01L29/78642

摘要： Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 公开了一种半导体器件制造方法，其包括以下步骤：在平面半导体层上形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方的所述平面状半导体层的一部分中形成第二导电型半导体层; 在所述柱状的第一导电型半导体层周围形成具有金属膜和非晶硅或多晶硅膜的叠层结构的栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅电极的顶部接触的侧壁状的电介质膜; 在所述栅电极的侧壁上形成第一和第二侧壁状电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成金属 - 半导体化合物; 在栅电极上形成金属 - 半导体化合物; 在形成在柱状第一导电型半导体层下方的平面状半导体层的部分的第二导电型半导体层上形成接触; 并且在形成在柱状第一导电型半导体层的上部的第二导电型半导体层上形成接触。

公开(公告)号：US08211758B2

公开(公告)日：2012-07-03

申请号：US12699611

申请日：2010-02-03

申请人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

发明人： Fujio Masuoka ,  Shintaro Arai ,  Hiroki Nakamura ,  Tomohiko Kudo

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66772

摘要： It is an object to provide an SGT production method capable of obtaining a structure for reducing a resistance of a gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor. The object is achieved by a semiconductor device production method which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate; forming a sidewall-shaped dielectric film on a sidewall of the gate; and forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer and on the second-conductive-type semiconductor layer formed underneath the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 本发明的目的是提供一种能够获得用于降低栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及柱状半导体的期望直径的结构的SGT制造方法。 该目的通过一种半导体器件制造方法来实现，该方法包括以下步骤：形成柱状的第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成栅极电介质膜和栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极的顶部接触的侧壁状的电介质膜; 在所述浇口的侧壁上形成侧壁状的电介质膜; 以及在柱状第一导电型半导体层的上部和形成在柱状的第一导电型半导体层下方的第二导电型半导体层上形成第二导电型半导体层。

公开(公告)号：US20100210079A1

公开(公告)日：2010-08-19

申请号：US12704004

申请日：2010-02-11

申请人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

发明人： Fujio Masuoka ,  Tomohiko Kudo ,  Shintaro Arai ,  Hiroki Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L29/42392 ,  H01L29/66666

摘要： It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode.

摘要翻译： 旨在提供一种能够获得用于降低源极，漏极和栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及要获得的柱状半导体的期望直径的结构的SGT制造方法。 该方法包括以下步骤：形成柱状第一导电型半导体层; 在所述柱状第一导电型半导体层的下方形成第二导电型半导体层; 在柱状第一导电型半导体层周围形成虚拟栅极电介质膜和虚拟栅电极; 在所述柱状第一导电型半导体层的侧壁的上部区域上形成与所述栅极电极的顶部接触的第一电介质膜，通过栅极电介质膜形成; 在所述栅电极的侧壁上形成第一电介质膜; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在柱状第一导电型半导体层的上部形成第二导电型半导体层; 在形成在柱状第一导电型半导体层的上部和下方的每个第二导电型半导体层上形成金属 - 半导体化合物; 去除伪栅极电介质膜和伪栅电极并形成高k栅极电介质膜和金属栅电极。