公开(公告)号：US20140273423A1

公开(公告)日：2014-09-18

申请号：US13798616

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jody A. Fronheiser ,  Jeremy A. Wahl ,  Kerem Akarvardar ,  Ajey P. Jacob ,  Daniel T. Pham

IPC: H01L29/66

CPC classification number: H01L29/42392 ,  B82Y40/00 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成具有至少30％的锗浓度的硅/锗层，形成多个间隔开的沟槽，其延伸穿过硅/锗层并且至少部分地进入半导体 衬底，其中所述沟槽限定由所述衬底的一部分和所述硅/锗层的一部分组成的器件的鳍结构，所述硅/锗层的所述部分具有第一横截面构造，形成层 的绝缘材料在沟槽中并在鳍结构之上，对器件进行退火处理，以使硅/锗层的第一截面构型变为不同于第二截面结构 第一横截面构造，以及围绕具有第二横截面的硅/锗层的至少一部分形成最终栅极结构 功能配置

公开(公告)号：US20140120677A1

公开(公告)日：2014-05-01

申请号：US13663854

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel T. Pham ,  Robert J. Miller ,  Kungsuk Maitra

IPC: H01L21/265 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/26506 ,  H01L29/66795 ,  H01L29/7842

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract translation: 本文公开了通过使用外延形成的材料在3D半导体器件（例如FinFET半导体器件）上形成应力沟道区的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定器件的鳍片的至少一部分，以及执行外延沉积工艺以形成外延形成的应力诱导材料 在壕沟里