公开(公告)号：US09466491B2

公开(公告)日：2016-10-11

申请号：US14268579

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Hyun-Jin Cho ,  Ruilong Xie

IPC: H01L21/28 ,  H01L21/283 ,  H01L29/423 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L21/28 ,  H01L21/28247 ,  H01L21/283 ,  H01L21/76897 ,  H01L29/417 ,  H01L29/41775 ,  H01L29/423 ,  H01L29/42364 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成侧壁隔离物，去除牺牲栅极结构并在其位置形成替代栅极结构 在形成替代栅极结构之后的某些点，执行蚀刻工艺以降低间隔物的高度，从而限定具有部分限定间隔物凹槽的上表面的凹进的间隔件，并且在上表面上形成间隔物蚀刻块帽 每个凹进的间隔结构和间隔凹槽内。

公开(公告)号：US09263585B2

公开(公告)日：2016-02-16

申请号：US13663854

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Robert J. Miller ,  Kungsuk Maitra

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7851 ,  H01L21/26506 ,  H01L29/66795 ,  H01L29/7842

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract translation: 本文公开了通过使用外延形成的材料在3D半导体器件（例如FinFET半导体器件）上形成应力沟道区的各种方法。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定器件的鳍片的至少一部分，以及执行外延沉积工艺以形成外延形成的应力诱导材料 在壕沟里

公开(公告)号：US08728885B1

公开(公告)日：2014-05-20

申请号：US13728438

申请日：2012-12-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Jody Fronheiser ,  William J. Taylor, Jr.

IPC: H01L29/94

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7846 ,  H01L29/78696

Abstract: One method herein includes forming a plurality of spaced-apart trenches that extend at least partially into a semiconducting substrate, wherein the trenches define a fin structure comprised of first and second layers of semiconducting material, wherein the first layer of semiconducting material is selectively etchable relative to the substrate and the second layer of semiconducting material, forming a sacrificial gate structure above the fin, wherein the gate structure includes a gate insulation layer and a gate electrode, forming a sidewall spacer adjacent the gate structure, performing an etching process to remove the sacrificial gate structure, thereby defining a gate cavity, performing at least one selective etching process to selectively remove the first layer of semiconducting material relative to the second layer of semiconducting material within the gate cavity, thereby defining a space between the second semiconducting material and the substrate, and forming a final gate structure in the gate cavity.

Abstract translation: 这里的一种方法包括形成多个间隔开的沟槽，其至少部分地延伸到半导体衬底中，其中沟槽限定由第一和第二半导体材料层组成的鳍结构，其中第一层半导体材料是相对于可选择地蚀刻的 到所述衬底和所述第二半导体材料层，在所述鳍片之上形成牺牲栅极结构，其中所述栅极结构包括栅极绝缘层和栅电极，形成邻近所述栅极结构的侧壁隔离层，执行蚀刻工艺以去除所述栅极结构 牺牲栅极结构，从而限定栅极腔，执行至少一个选择性蚀刻工艺，以相对于栅极腔内的第二半导体材料层选择性地去除第一半导体材料层，由此限定第二半导体材料与第二半导体材料之间的空间 衬底，并形成最终的门结构 在门洞里。

公开(公告)号：US09064932B1

公开(公告)日：2015-06-23

申请号：US14268478

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Zhenyu Hu

IPC: H01L21/70 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L21/76838 ,  H01L21/76865 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795

Abstract: One method disclosed includes, among other things, forming an uncut line-type gate structure above first and second spaced-apart active regions of a semiconductor substrate, forming a sidewall spacer around a perimeter of the line-type gate structure, performing at least one etching process to remove an axial portion of a gate cap layer and an axial portion of a gate electrode that are positioned above the isolation region so as to thereby define first and second cut end surfaces of first and second gate electrodes, respectively, and an isolation plug cavity and forming a gate cut isolation plug in the isolation plug cavity.

Abstract translation: 所公开的一种方法包括在半导体衬底的第一和第二间隔开的有源区之上形成未切割线型栅极结构，在线型栅极结构的周边上形成侧壁隔离物，执行至少一个 蚀刻工艺以去除位于隔离区域上方的栅极盖层和栅电极的轴向部分的轴向部分，从而分别限定第一和第二栅电极的第一和第二切割端表面，以及隔离 插塞腔并在隔离插塞腔中形成栅极切割隔离插头。

公开(公告)号：US20140225168A1

公开(公告)日：2014-08-14

申请号：US13764115

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, JR. ,  Robert Miller

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

公开(公告)号：US08877588B2

公开(公告)日：2014-11-04

申请号：US13764115

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Werner Juengling ,  William J. Taylor, Jr. ,  Robert Miller

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: One method includes forming first and second spaced-apart trenches extending at least partially into a semiconducting substrate defining a fin structure for the device, forming a stress-inducing material having a first type of stress in the first trench, forming a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different than the first type of stress, and forming a gate structure around a portion of the fin structure. One device includes first and second spaced-apart trenches in a semiconducting substrate defining at least a portion of a fin for the device, a stress-inducing material having a first type of stress in the first trench, a second stress-inducing material in the second trench, the second stress-inducing material having a second stress that is a different type than the first stress, and a gate structure around a portion of the fin structure.

Abstract translation: 一种方法包括形成第一和第二间隔开的沟槽，其至少部分延伸到限定用于器件的鳍结构的半导体衬底中，形成在第一沟槽中具有第一类型应力的应力诱导材料，形成第二应力诱导 第二沟槽中的材料，第二应力诱导材料具有不同于第一类型应力的第二应力，以及围绕鳍结构的一部分形成栅极结构。 一个器件包括在半导体衬底中限定用于器件的鳍片的至少一部分的第一和第二间隔开的沟槽，在第一沟槽中具有第一类型应力的应力诱导材料，在第一沟槽中的第二应力诱导材料 第二沟槽，第二应力诱导材料具有与第一应力不同的第二应力，以及围绕鳍结构的一部分的栅极结构。

公开(公告)号：US08853019B1

公开(公告)日：2014-10-07

申请号：US13798616

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Jeremy A. Wahl ,  Kerem Akarvardar ,  Ajey P. Jacob ,  Daniel T. Pham

IPC: H01L29/94 ,  H01L29/66 ,  B82Y40/00

CPC classification number: H01L29/42392 ,  B82Y40/00 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成具有至少30％的锗浓度的硅/锗层，形成多个间隔开的沟槽，其延伸穿过硅/锗层并且至少部分地进入半导体 衬底，其中所述沟槽限定由所述衬底的一部分和所述硅/锗层的一部分组成的器件的鳍结构，所述硅/锗层的所述部分具有第一横截面构造，形成层 的绝缘材料在沟槽中并在鳍结构之上，对器件进行退火处理，以使硅/锗层的第一截面构型变为不同于第二截面结构 第一横截面构造，以及围绕具有第二横截面的硅/锗层的至少一部分形成最终栅极结构 功能配置

公开(公告)号：US09184263B2

公开(公告)日：2015-11-10

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。

公开(公告)号：US20150318178A1

公开(公告)日：2015-11-05

申请号：US14268579

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel T. Pham ,  Hyun-Jin Cho ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/417 ,  H01L21/283

CPC classification number: H01L21/28 ,  H01L21/28247 ,  H01L21/283 ,  H01L21/76897 ,  H01L29/417 ,  H01L29/41775 ,  H01L29/423 ,  H01L29/42364 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial gate structure above a semiconductor substrate, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure and forming a replacement gate structure in its place, at some point after forming the replacement gate structure, performing an etching process to reduce the height of the spacers so as to thereby define recessed spacers having an upper surface that partially defines a spacer recess, and forming a spacer etch block cap on the upper surface of each recessed spacer structure and within the spacer recess.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成牺牲栅极结构，在牺牲栅极结构的相对侧面上形成侧壁隔离物，去除牺牲栅极结构并在其位置形成替代栅极结构 在形成替代栅极结构之后的某些点，执行蚀刻工艺以降低间隔物的高度，从而限定具有部分限定间隔物凹槽的上表面的凹进的间隔件，并且在上表面上形成间隔物蚀刻块帽 每个凹进的间隔结构和间隔凹槽内。

公开(公告)号：US20150187905A1

公开(公告)日：2015-07-02

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/417

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。