公开(公告)号：US09443951B2

公开(公告)日：2016-09-13

申请号：US14076387

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/66484 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

公开(公告)号：US20160379986A1

公开(公告)日：2016-12-29

申请号：US15160482

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Wilfried E. Haensch

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10867 ,  H01L21/845 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1207 ,  H01L29/0673 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/785

Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

公开(公告)号：US20160276570A1

公开(公告)日：2016-09-22

申请号：US14659749

申请日：2015-03-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Paul Chang ,  Guy M. Cohen ,  Michael A. Guillorn

IPC: H01L39/02 ,  H01L39/24 ,  H01L39/22

CPC classification number: H01L39/025 ,  B05D5/12 ,  H01L39/223 ,  H01L39/2467 ,  H01L39/2493

Abstract: Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure.

Abstract translation: 硅石纳米线作为约瑟夫逊结中的纳米桥。 在约瑟夫逊结中使用超导硅化物纳米线作为弱连接桥，并且制造工艺用于制造硅化物纳米线，其包括从硅衬底图案化两个连接堤和粗糙的纳米线，通过氢退火重新形成纳米线，以及 通过在纳米线结构中引入金属来硅化纳米线。