公开(公告)号：US09437443B2

公开(公告)日：2016-09-06

申请号：US13916109

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Markus Brink ,  Michael A. Guillorn ,  Sebastian U. Engelmann ,  Hiroyuki Miyazoe ,  Adam M. Pyzyna ,  Jeffrey W. Sleight

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3088 ,  H01L21/32139

Abstract: A SIT method includes the following steps. An SIT mandrel material is deposited onto a substrate and formed into a plurality of SIT mandrels. A spacer material is conformally deposited onto the substrate covering a top and sides of each of the SIT mandrels. Atomic Layer Deposition (ALD) is used to deposit the SIT spacer at low temperatures. The spacer material is selected from the group including a metal, a metal oxide, a metal nitride and combinations including at least one of the foregoing materials. The spacer material is removed from all but the sides of each of the SIT mandrels to form SIT sidewall spacers on the sides of each of the SIT mandrels. The SIT mandrels are removed selective to the SIT sidewall spacers revealing a pattern of the SIT sidewall spacers. The pattern of the SIT sidewall spacers is transferred to the underlying stack or substrate.

Abstract translation: SIT方法包括以下步骤。 将SIT芯棒材料沉积到衬底上并形成多个SIT芯棒。 间隔物材料被共形沉积到基底上，覆盖每个SIT心轴的顶部和侧面。 原子层沉积（ALD）用于在低温下沉积SIT间隔物。 间隔材料选自金属，金属氧化物，金属氮化物和包括至少一种前述材料的组合。 隔离材料从每个SIT心轴的所有侧面除去，以在每个SIT心轴的侧面上形成SIT侧壁间隔物。 SIT心轴被选择性地移除到SIT侧壁间隔件上，露出SIT侧壁间隔物的图案。 SIT侧壁间隔物的图案被转移到下面的堆叠或衬底。

公开(公告)号：US09209086B2

公开(公告)日：2015-12-08

申请号：US13947316

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/66439 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques for integrating low temperature salicide formation in a replacement gate device process flow are provided. In one aspect, a method of fabricating a FET device is provided that includes the following steps. A dummy gate(s) is formed over an active area of a wafer. A gap filler material is deposited around the dummy gate. The dummy gate is removed selective to the gap filler material, forming a trench in the gap filler material. A replacement gate is formed in the trench in the gap filler material. The replacement gate is recessed below a surface of the gap filler material. A gate cap is formed in the recess above the replacement gate. The gap filler material is etched back to expose at least a portion of the source and drain regions of the device. A salicide is formed on source and drain regions of the device.

Abstract translation: 提供了在替代浇口装置工艺流程中集成低温自对准硅化物形成技术。 一方面，提供了一种制造FET器件的方法，包括以下步骤。 在晶片的有效区域上形成虚拟栅极。 间隙填充材料沉积在虚拟栅极周围。 虚拟栅极被选择性地移除到间隙填充材料上，在间隙填充材料中形成沟槽。 在间隙填充材料的沟槽中形成替换栅极。 更换浇口凹陷在间隙填充材料的表面下方。 在替换门上方的凹槽中形成栅极盖。 间隙填充材料被回蚀以暴露该器件的源极和漏极区域的至少一部分。 在设备的源极和漏极区域上形成自对准硅化物。

公开(公告)号：US20170250111A1

公开(公告)日：2017-08-31

申请号：US15593496

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US09559284B2

公开(公告)日：2017-01-31

申请号：US14659749

申请日：2015-03-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Paul Chang ,  Guy M. Cohen ,  Michael A. Guillorn

IPC: B05D5/12 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24

CPC classification number: H01L39/025 ,  B05D5/12 ,  H01L39/223 ,  H01L39/2467 ,  H01L39/2493

Abstract: Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure.

Abstract translation: 硅石纳米线作为约瑟夫逊结中的纳米桥。 在约瑟夫逊结中使用超导硅化物纳米线作为弱连接桥，并且制造工艺用于制造硅化物纳米线，其包括从硅衬底图案化两个连接堤和粗糙的纳米线，通过氢退火重新形成纳米线，以及 通过在纳米线结构中引入金属来硅化纳米线。

公开(公告)号：US09385026B2

公开(公告)日：2016-07-05

申请号：US14272691

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate.

Abstract translation: 一方面，用于形成开尔文可测试结构的基于DSA的方法包括以下步骤。 引导图案形成在衬底上，其限定i）开尔文可测试结构的多个焊盘区域，以及ii）将衬底上的两个衬垫区域互连的区域。 自组装材料沉积在衬底上，并在足以使其经历自组装以在衬底上形成自组装图案的温度/持续时间退火，其中自组装由引导图案引导 互连两个焊盘区域的区域中的自组装材料形成多个直线。 自组装材料的图案被转移到在衬底中形成多条线的衬底，其中自组装材料的图案被配置为使得只有给定的一条线是两个焊盘区域之间的连续线 底物。

公开(公告)号：US09337264B2

公开(公告)日：2016-05-10

申请号：US14664435

申请日：2015-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sarunya Bangsaruntip ,  Guy Cohen ,  Michael A. Guillorn

IPC: H01L29/786 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/165 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/0669 ,  B82Y10/00 ,  H01L21/28518 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/78645 ,  H01L29/78696

Abstract: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

公开(公告)号：US09385027B2

公开(公告)日：2016-07-05

申请号：US14811236

申请日：2015-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate.

公开(公告)号：US10014214B2

公开(公告)日：2018-07-03

申请号：US15593496

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12 ,  H01L21/74 ,  H01L23/535

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US09716036B2

公开(公告)日：2017-07-25

申请号：US14733398

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US20160358852A1

公开(公告)日：2016-12-08

申请号：US14733398

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract translation: 提供电子设备。 电子器件包括半导体层，设置在半导体层上的电介质层，设置在电介质层上的电路，包括互连电池，第一接触线金属化和第二接触线金属化，第一电力金属化设置在电路内或电路之上 以及设置在至少所述介电层中限定的沟槽中的第二功率金属化。 电子设备还包括绝缘体，其设置成在第一位置处将第二功率金属化与电路和第一功率金属化绝缘，并且允许在第二位置处的第二功率金属化，电路和第一功率金属化之间的电通信。