公开(公告)号：US09330221B2

公开(公告)日：2016-05-03

申请号：US14286395

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules.

Abstract translation: 公开了基于掩模设计规则和所得到的设备来布线金属路由层的方法。 实施例可以包括在半导体设计布局中布置连续金属线，以及根据切割或块掩模设计规则，根据切割或块掩模的放置，利用处理器路由使用连续金属线的金属布线层。

公开(公告)号：US09437588B1

公开(公告)日：2016-09-06

申请号：US14742935

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L29/66 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L2027/11875

Abstract: A dense library architecture using an M0 hand-shake and the method of forming the layout are disclosed. Embodiments include forming first and second active areas on a substrate, at the top and bottom of a cell, separated from each other; forming first through third gate lines perpendicular to the active areas, where the first and third gate lines are dummy gates at the cell edges; forming trench silicide segments on each of the active areas, between the first, second, and third gate lines; forming first and second M1 metal lines between the first and second gate lines and the second and third gate lines, respectively; forming a M0 segment between the first and second active regions perpendicular to the M1 metal lines; forming a CB between the M0 segment and the second gate line; and forming a V0 from the first metal line to the M0 segment.

Abstract translation: 公开了使用M0手摇的密集库结构和形成布局的方法。 实施例包括在基板上，在电池的顶部和底部形成彼此分离的第一和第二有源区; 形成垂直于有源区的第一至​​第三栅极线，其中第一和第三栅极线在单元边缘处是伪栅极; 在所述第一，第二和第三栅极线之间的所述有源区域中的每一个上形成沟槽硅化物段; 在第一和第二栅极线与第二和第三栅极线之间分别形成第一和第二M1金属线; 在垂直于M1金属线的第一和第二有源区之间形成M0段; 在M0段和第二栅极线之间形成CB; 并从第一金属线形成V0至M0段。

公开(公告)号：US20150243515A1

公开(公告)日：2015-08-27

申请号：US14186396

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/306 ,  G06F17/50

CPC classification number: H01L21/3088 ,  G03F1/70 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.

Abstract translation: 一种涉及识别用于构图线型特征的整体目标切割掩模的图案的方法，所述线型特征包括具有内凹角的目标非矩形开口特征，将总体目标切割掩模图案分解为第一和第二子图， 目标图案，其中所述第一子目标图案包括与所述目标非矩形开口特征和所述第二子目标图案的第一部分但不是全部相对应的第一矩形开口特征，所述第一子目标图案包括第二矩形开口特征， 特征对应于目标非矩形开口特征的第二部分但不是全部，第一和第二开口与内凹角相邻重叠，并且生成对应于第一和第二子图的第一和第二组掩模数据， 目标图案，其中基于所识别的切割线间距规则，生成第一组和第二组掩模数据中的至少一个。

公开(公告)号：US08966412B1

公开(公告)日：2015-02-24

申请号：US14035329

申请日：2013-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70283 ,  G03F7/70466

Abstract: One method disclosed herein involves, among other things, identifying a plurality of features within an overall pattern layout that cannot be decomposed using the SADP process, wherein at least first and second adjacent features are required to be same-color features, decreasing a spacing between the first and second adjacent features such that the first feature and the second feature become different-color features so as to thereby render the plurality of features decomposable using the SADP process, decomposing the overall pattern layout into a mandrel mask pattern and a block mask pattern, and generating mask data sets corresponding to the mandrel mask pattern and the block mask pattern.

Abstract translation: 本文公开的一种方法除其他外包括识别不能使用SADP过程分解的整体图案布局中的多个特征，其中至少第一和第二相邻特征需要是相同颜色的特征， 所述第一和第二相邻特征使得所述第一特征和所述第二特征变为不同颜色特征，从而使得所述多个特征可以使用所述SADP处理分解，将所述整体图案布局分解为心轴掩模图案和块掩模图案 并且生成与心轴掩模图案和块掩模图案相对应的掩模数据集。

公开(公告)号：US08918746B1

公开(公告)日：2014-12-23

申请号：US14018074

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  G01N23/00 ,  G03F1/00 ,  H01L21/00

CPC classification number: H01L27/0207

Abstract: Methodologies and an apparatus enabling a selection of design rules to improve a density of features of an IC design are disclosed. Embodiments include: determining a feature overlapping a grating pattern of an IC design, the grating pattern including a plurality of grating structures; determining a shape of a cut pattern overlapping the grating pattern; and selecting one of a plurality of rules for the feature based on the determined shape.

Abstract translation: 公开了能够选择设计规则以提高IC设计的特征密度的方法和装置。 实施例包括：确定与IC设计的光栅图案重叠的特征，所述光栅图案包括多个光栅结构; 确定与所述光栅图案重叠的切割图案的形状; 以及基于所确定的形状来选择所述特征的多个规则中的一个。

公开(公告)号：US20140208285A1

公开(公告)日：2014-07-24

申请号：US13746508

申请日：2013-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jongwook Kye ,  Harry J. Levinson ,  Jason E. Stephens ,  Lei Yuan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.

Abstract translation: 公开了一种用于确定与自对准双重图案（SADP）技术一起使用的通孔外壳规则的设计方法。 块掩模的形状作为选择通孔封套规则的标准。 集成电路设计中不同的块掩模形状可以利用不同的规则，并为通孔外壳提供不同的边缘。 紧密的通孔外壳设计规则可能会减少超出通孔的线的余量，而松动的通孔外壳设计规则可增加超出通孔的线的裕度，从而有利于此。