公开(公告)号：US10157777B2

公开(公告)日：2018-12-18

申请号：US15152797

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L23/66 ,  H01L29/786

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US09673220B1

公开(公告)日：2017-06-06

申请号：US15065331

申请日：2016-03-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Randy L. Wolf ,  Mark D. Jaffe

IPC: H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/417 ,  H01L29/08 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/683 ,  H01L21/768

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/4175 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78618

Abstract: Chip structures that include distributed wiring layouts and fabrication methods for forming such chip structures. A device structure is formed that includes a plurality of first device regions and a plurality of second device regions. A first wiring level is formed that includes a first wire coupled with the first device regions. A second wiring level is formed that includes a second wire coupled with the second device regions. The first wiring level is vertically separated from the second wiring level by a buried oxide layer of the silicon-on-insulator substrate.