公开(公告)号：US20240063309A1

公开(公告)日：2024-02-22

申请号：US17892205

申请日：2022-08-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  James A. Cooper

IPC: H01L29/808 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/808 ,  H01L29/1608 ,  H01L29/66068

Abstract: Structures for a junction field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a trench, and a source including a doped region in the semiconductor substrate adjacent to the trench. The doped region and the semiconductor substrate have the same conductivity type. The doped region has a first boundary adjacent to a surface of the semiconductor substrate and a second boundary spaced in depth from the first boundary. The structure further comprises a gate structure including a conductor layer inside the trench and a dielectric layer inside the trench. The first conductor layer has a surface positioned between the first boundary of the doped region and the second boundary of the doped region, and the dielectric layer is positioned on the surface of the conductor layer.

公开(公告)号：US20240063219A1

公开(公告)日：2024-02-22

申请号：US17819980

申请日：2022-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Jerry Joseph James ,  Steven J. Bentley ,  Francois Hebert ,  Richard J. Rassel

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L27/0883 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/401 ,  H01L29/402 ,  H01L29/0607

Abstract: A structure for an III-V integrated circuit includes an integrated depletion and enhancement mode gallium nitride high electron mobility transistors (HEMTs). The structure includes a first, depletion mode HEMT having a first source, a first drain and a first fieldplate gate between the first source and the first drain, and a second, enhancement mode HEMT having a second source and a second drain. The second HEMT also includes a gallium nitride (GaN) gate and a second fieldplate gate between the second source and the second drain. The second fieldplate gate of the second HEMT may be closer to the second drain than the GaN gate. The structure provides a reliable, low leakage, high voltage depletion mode HEMT (e.g., with operating voltages of greater than 100V, but with a pinch-off voltage of less than 6 Volts) integrated with a gallium nitride (GaN) gate-based enhancement mode HEMT.

公开(公告)号：US11784189B2

公开(公告)日：2023-10-10

申请号：US17407680

申请日：2021-08-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Francois Hebert ,  Handoko Linewih

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

公开(公告)号：US20240258421A1

公开(公告)日：2024-08-01

申请号：US18103776

申请日：2023-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer in the trench, and a dielectric layer on the top surface of the semiconductor substrate. The dielectric layer includes an opening that is aligned with the trench in the semiconductor substrate, and the dielectric layer comprises a material with a melting point that is greater than or equal to 2000° C.

公开(公告)号：US20230059665A1

公开(公告)日：2023-02-23

申请号：US17407680

申请日：2021-08-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Francois Hebert ,  Handoko Linewih

IPC: H01L27/12 ,  H01L21/84

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.