公开(公告)号：US07007156B2

公开(公告)日：2006-02-28

申请号：US09751943

申请日：2000-12-28

Applicant: Gavin J. Stark ,  John Wishneusky

Inventor： Gavin J. Stark ,  John Wishneusky

IPC: G06F9/00

CPC classification number: G06F9/5044 ,  G06F2209/5017

Abstract: A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.

Abstract translation: 一种编程状态处理机架构和方法，可提高处理数据操作任务的效率。 在一个实施例中，处理机包括控制引擎和多个协处理器，数据存储器和指令存储器。 具有多个部分的指令序列由指令存储器发出，其中使控制引擎和每个处理器基于为该部件指定的指令的部分执行特定任务。 因此，数据操作任务可以被划分成由架构中的各个处理组件并行处理的多个子任务。

公开(公告)号：US09626306B2

公开(公告)日：2017-04-18

申请号：US13399983

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Jarod L. Oatley ,  Michael D. Secules ,  Ronald N. Fortino

Inventor： Gavin J. Stark ,  Jarod L. Oatley ,  Michael D. Secules ,  Ronald N. Fortino

IPC: G06F13/42 ,  G06F13/00 ,  G06F13/40

CPC classification number: G06F13/00 ,  G06F13/4022

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information.

公开(公告)号：US09268600B2

公开(公告)日：2016-02-23

申请号：US13970601

申请日：2013-08-20

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F15/163

CPC classification number: G06F9/467 ,  G06F15/163 ,  H04L45/745 ,  H04L45/7457

Abstract: A transactional memory (TM) includes a selectable bank of hardware algorithm prework engines, a selectable bank of hardware lookup engines, and a memory unit. The memory unit stores result values (RVs), instructions, and lookup data operands. The transactional memory receives a lookup command across a bus from one of a plurality of processors. The lookup command includes a source identification value, data, a table number value, and a table set value. In response to the lookup command, the transactional memory selects one hardware algorithm prework engine and one hardware lookup engine to perform the lookup operation. The selected hardware algorithm prework engine modifies data included in the lookup command. The selected hardware lookup engine performs a lookup operation using the modified data and lookup operands provided by the memory unit. In response to performing the lookup operation, the transactional memory returns a result value and optionally an instruction.

Abstract translation: 事务存储器（TM）包括可选择的硬件算法预处理引擎组，可选择的硬件查找引擎组和存储器单元。 存储单元存储结果值（RV），指令和查找数据操作数。 事务存储器从多个处理器之一接收总线上的查找命令。 查找命令包括源标识值，数据，表号值和表设置值。 响应于查找命令，事务存储器选择一个硬件算法预处理引擎和一个硬件查找引擎来执行查找操作。 所选的硬件算法预处理引擎修改查找命令中包含的数据。 所选择的硬件查找引擎使用由存储器单元提供的经修改的数据和查找操作数来执行查找操作。 响应于执行查找操作，事务存储器返回结果值和可选的指令。

公开(公告)号：US09071545B2

公开(公告)日：2015-06-30

申请号：US13668251

申请日：2012-11-03

Applicant: Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen ,  Rolf Neugebauer

Inventor： Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen ,  Rolf Neugebauer

IPC: H04L12/861 ,  H04L12/725 ,  H04L12/851 ,  H04L12/26

CPC classification number: H04L45/30 ,  H04L43/0852 ,  H04L47/245 ,  H04L47/283

Abstract: A network appliance includes a network processor and several processing units. Packets a flow pair are received onto the network appliance. Without performing deep packet inspection on any packet of the flow pair, the network processor analyzes the flows, estimates therefrom the application protocol used, and determines a predicted future time when the next packet will likely be received. The network processor determines to send the next packet to a selected one of the processing units based in part on the predicted future time. In some cases, the network processor causes a cache of the selected processing unit to be preloaded shortly before the predicted future time. When the next packet is actually received, the packet is directed to the selected processing unit. In this way, packets are directed to processing units within the network appliance based on predicted future packet arrival times without the use of deep packet inspection.

Abstract translation: 网络设备包括网络处理器和多个处理单元。 将流对的数据包接收到网络设备上。 网络处理器不对流对的任何数据包进行深度数据包检测，从而分析流量，从而估算所使用的应用协议，并确定下一个数据包可能被接收时的预测未来时间。 部分地基于预测的未来时间，网络处理器确定将下一个分组发送到所选择的一个处理单元。 在一些情况下，网络处理器使所选择的处理单元的高速缓存在预测的未来时间之前不久被预加载。 当实际接收到下一个分组时，分组被引导到所选择的处理单元。 以这种方式，基于预测的未来分组到达时间，分组被定向到网络设备内的处理单元，而不使用深度分组检查。

公开(公告)号：US09069649B2

公开(公告)日：2015-06-30

申请号：US13399846

申请日：2012-02-17

Applicant: Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

IPC: G06F13/00 ,  H04L12/801 ,  H04L12/879

CPC classification number: G06F13/4022 ,  G06F13/00 ,  H04L47/39 ,  H04L49/901

Abstract: An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar switch and radiating half links. The half links of adjacent islands align to form links between crossbar switches. A link is implemented as two distributed credit FIFOs. In one direction, a link portion involves a FIFO associated with an output port of a first island, a first chain of registers, and a second FIFO associated with an input port of a second island. When a transaction value passes through the FIFO and through the crossbar switch of the second island, an arbiter in the crossbar switch returns a taken signal. The taken signal passes back through a second chain of registers to a credit count circuit in the first island. The credit count circuit maintains a credit count value for the distributed credit FIFO.

Abstract translation: 基于岛的集成电路包括可配置的网状数据总线。 数据总线包括四个网格。 每个网格对于每个岛包括一个交叉开关和辐射半连接。 相邻岛屿的半连接对齐以形成交叉开关之间的连接。 链接被实现为两个分布式信用FIFO。 在一个方向上，链接部分涉及与第一岛的输出端口，第一寄存器链和与第二岛的输入端口相关联的第二FIFO相关联的FIFO。 当交易值通过FIFO并通过第二岛的交叉开关时，交叉开关中的仲裁器返回一个取得的信号。 所采集的信号通过第二个寄存器链回到第一个岛的信用计数电路。 信用计数电路维持分配信用FIFO的信用计数值。

公开(公告)号：US09042252B2

公开(公告)日：2015-05-26

申请号：US13675620

申请日：2012-11-13

Applicant: Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen

Inventor： Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen

IPC: H04L12/28 ,  H04L29/06 ,  H04J3/00

CPC classification number: H04B10/0799 ,  H04L29/06 ,  H04L41/142 ,  H04L47/2441 ,  H04L47/2483 ,  H04L69/22 ,  H04L69/28

Abstract: An appliance receives packets that are part of a flow pair, each packet sharing an application protocol. The appliance determines the application protocol of the packets by performing deep packet inspection (DPI) on the packets. Packet sizes are measured and converted into packet size states. Packet size states, packet sequence numbers, and packet flow directions are used to create an application protocol estimation table (APET). The APET is used during normal operation to estimate the application protocol of a flow pair without performing time consuming DPI. The appliance then determines inter-packet intervals between received packets. The inter-packet intervals are converted into inter-packet interval states. The inter-packet interval states and packet sequence numbers are used to create an inter-packet interval prediction table. The appliance then stores an inter-packet interval prediction table for each application protocol. The inter-packet interval prediction table is used during operation to predict the inter-packet interval between packets.

Abstract translation: 设备接收作为流对的一部分的数据包，每个数据包共享一个应用协议。 设备通过对数据包执行深度数据包检测（DPI）来确定数据包的应用协议。 数据包大小被测量并转换成数据包大小状态。 分组大小状态，分组序列号和分组流方向用于创建应用协议估计表（APET）。 在正常操作期间使用APET来估计流对的应用协议，而不执行耗时的DPI。 然后，设备确定接收到的分组之间的分组间间隔。 分组间间隔被转换成分组间间隔状态。 分组间间隔状态和分组序列号用于创建分组间间隔预测表。 然后，设备为每个应用协议存储分组间间隔预测表。 在操作期间使用分组间间隔预测表来预测分组之间的分组间间隔。

公开(公告)号：US20140153571A1

公开(公告)日：2014-06-05

申请号：US13690195

申请日：2012-11-30

Applicant: Rolf Neugebauer ,  Gavin J. Stark ,  Espen Skoglund

Inventor： Rolf Neugebauer ,  Gavin J. Stark ,  Espen Skoglund

IPC: H04L12/56

CPC classification number: H04L47/18 ,  H04L45/7453 ,  H04L45/7457 ,  H04L47/32 ,  H04L47/34

Abstract: A flow key is determined from an incoming packet. Two hash values A and B are then generated from the flow key. Hash value A is an index into a hash table to identify a hash bucket. Multiple simultaneous CAM lookup operations are performed on fields of the bucket to determine which ones of the fields store hash value B. For each populated field there is a corresponding entry in a key table and in other tables. The key table entry corresponding to each field that stores hash value B is checked to determine if that key table entry stores the original flow key. When the key table entry that stores the original flow key is identified, then the corresponding entries in the other tables are determined to be a “lookup output information value”. This value indicates how the packet is to be handled/forwarded by the network appliance.

Abstract translation: 从输入包确定流密钥。 然后从流密钥生成两个散列值A和B. 哈希值A是哈希表中用于标识哈希桶的索引。 在桶的字段上执行多个同时的CAM查找操作，以确定哪些字段存储散列值B.对于每个填充字段，在键表和其他表中都有相应的条目。 检查对应于存储散列值B的每个字段的密钥表条目，以确定该密钥表条目是否存储原始流密钥。 当存储原始流密钥的密钥表条目被识别时，其他表中的相应条目被确定为“查找输出信息值”。 该值指示如何由网络设备处理/转发数据包。

公开(公告)号：US20140136814A1

公开(公告)日：2014-05-15

申请号：US13675259

申请日：2012-11-13

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/10

CPC classification number: G06F9/526 ,  G06F9/34 ,  G06F9/467 ,  G06F13/00 ,  G06F17/30

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple threshold values (TVs) from memory. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The multiple TVs define multiple lookup key ranges. The TM determines which lookup key range includes the LKV. A RV is selected based upon the lookup key range determined to include the LKV. The lookup key range is determined by a lookup key range identifier circuit. The selected RV is selected by a result value selection circuit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括存储器地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV）和多个阈值（TV）的单词。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是查询键值（LKV）。 多台电视定义了多个查找键范围。 TM确定哪个查找键范围包括LKV。 基于确定为包括LKV的查找关键字范围来选择RV。 查找键范围由查找键范围标识符电路确定。 所选择的RV由结果值选择电路选择。

公开(公告)号：US20130219103A1

公开(公告)日：2013-08-22

申请号：US13399324

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/14

CPC classification number: G06F13/4068 ,  G06F13/14 ,  G06F13/36 ,  G06F13/4022 ,  G06F17/5068

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. A configurable mesh data bus includes a command mesh, a pull-id mesh, and two data meshes. The configurable mesh data bus extends through all the islands. For each mesh, each island includes a centrally located crossbar switch and eight half links. Two half links extend to ports on the top edge of the island, a half link extends to a port on a right edge of the island, two half links extend to ports on the bottom edge of the island, and a half link extents to a port on the left edge of the island. Two additional links extend to functional circuitry of the island. The configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行排列的矩形岛。 可配置的网格数据总线包括命令网格，拉式网格和两个数据网格。 可配置的网格数据总线延伸穿过所有岛。 对于每个网格，每个岛包括一个位于中心的交叉开关和八个半连接。 两个半连杆延伸到岛的顶部边缘上的端口，半连接延伸到岛的右边缘上的端口，两个半连接延伸到岛的底部边缘上的端口，并且半连接范围到 港口在岛的左边缘。 两个额外的链路延伸到岛的功能电路。 可配置的网格数据总线可配置成形成一个命令/推/拉数据总线，多个事务可以同时发生在集成电路的不同部分上。

公开(公告)号：US06963535B2

公开(公告)日：2005-11-08

申请号：US09751936

申请日：2000-12-28

Applicant: Gavin J. Stark ,  John Wishneusky

Inventor： Gavin J. Stark ,  John Wishneusky

IPC: H04L12/413 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04L12/26

CPC classification number: H04L29/06 ,  H04L12/40032 ,  H04L69/324

Abstract: A Media Access Control (MAC) Bus interface definition and multiplexor scheme that may be implemented to provide chip layout-insensitive connections between a number of communication physical layer port entities and a single buffer manager or communications controller entity, utilizing a set of independent pipelined buses. The interface comprising three buses: A MAC In Data bus, a MAC Out Data bus, and a MAC Out Message bus. Each bus can operated with an independent set of timing signals to enable data transfers between a system side block and one or more network side blocks. The multiplexor scheme provides a multiplexor for each of the MAC buses, and enables a single system side block to connect to multiple network side blocks. The multiplexors may be also be cascaded.

Abstract translation: 媒体访问控制（MAC）总线接口定义和多路复用器方案，其可被实现以在多个通信物理层端口实体与单个缓冲器管理器或通信控制器实体之间提供芯片布局不敏感的连接，利用一组独立的流水线总线 。 该接口包括三条总线：MAC数据总线，MAC输出数据总线和MAC输出消息总线。 每个总线可以用独立的一组定时信号进行操作，以实现系统侧块和一个或多个网络侧块之间的数据传输。 多路复用器方案为每个MAC总线提供多路复用器，并使得单个系统侧块能够连接到多个网络侧块。 多路复用器也可以级联。