公开(公告)号：US11798948B2

公开(公告)日：2023-10-24

申请号：US17496296

申请日：2021-10-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Eric S. Kozarsky ,  George R. Mulfinger ,  Jianwei Peng

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/808

CPC classification number: H01L27/1203 ,  H01L21/7624 ,  H01L21/84 ,  H01L29/808

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

公开(公告)号：US11569268B1

公开(公告)日：2023-01-31

申请号：US17394770

申请日：2021-08-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/84 ,  H01L27/146 ,  H01L21/762 ,  H01L29/06

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US11450573B2

公开(公告)日：2022-09-20

申请号：US16903559

申请日：2020-06-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： George R. Mulfinger ,  Chung F. Tan ,  Ryan W. Sporer

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/02

Abstract: A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

公开(公告)号：US11127843B2

公开(公告)日：2021-09-21

申请号：US16733528

申请日：2020-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson Holt ,  Alexander Derrickson ,  Ryan Sporer ,  George R. Mulfinger ,  Alexander Martin ,  Jagar Singh

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/10

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.

公开(公告)号：US11094805B2

公开(公告)日：2021-08-17

申请号：US16745833

申请日：2020-01-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Edmund K. Banghart ,  Alexander Martin ,  Ryan Sporer ,  Jagar Singh ,  Katherina Babich ,  George R. Mulfinger

IPC: H01L29/737 ,  H01L29/08 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

公开(公告)号：US20210091212A1

公开(公告)日：2021-03-25

申请号：US16733528

申请日：2020-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson Holt ,  Alexander Derrickson ,  Ryan Sporer ,  George R. Mulfinger ,  Alexander Martin ,  Jagar Singh

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A base layer is positioned in a cavity in a semiconductor layer, a first terminal is coupled to the base layer, and a second terminal is coupled to a portion of the semiconductor layer. The second terminal is laterally spaced from the first terminal, and the portion of the semiconductor layer is laterally positioned between the second terminal and the base layer.